AuroraMiddleware/SPIRV-Cross-Vulnerable
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Fix regression from adding 64-bit switch support.

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Missed some cases where we did not handle the loaded type width
properly.
This commit is contained in:
Hans-Kristian Arntzen 2022-02-16 11:49:24 +01:00
parent 339e61a0e0
commit 29cc18988c
2 changed files with 14 additions and 2 deletions
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5
spirv_cross.cpp
View File

@ -1677,6 +1677,11 @@ const SmallVector<SPIRBlock::Case> &Compiler::get_case_list(const SPIRBlock &blo
const auto &type = get<SPIRType>(var->basetype);
width = type.width;
}
else if (const auto *undef = maybe_get<SPIRUndef>(block.condition))
{
const auto &type = get<SPIRType>(undef->basetype);
width = type.width;
}
else
{
auto search = ir.load_type_width.find(block.condition);

11
spirv_parser.cpp
View File

@ -291,7 +291,15 @@ void Parser::parse(const Instruction &instruction)
{
// The SPIR-V debug information extended instructions might come at global scope.
if (current_block)
{
current_block->ops.push_back(instruction);
if (length >= 2)
{
const auto *type = maybe_get<SPIRType>(ops[0]);
if (type)
ir.load_type_width.insert({ ops[1], type->width });
}
}
break;
}
@ -1211,10 +1219,9 @@ void Parser::parse(const Instruction &instruction)
{
const auto *type = maybe_get<SPIRType>(ops[0]);
if (type)
{
ir.load_type_width.insert({ ops[1], type->width });
}
}
if (!current_block)
SPIRV_CROSS_THROW("Currently no block to insert opcode.");