AuroraMiddleware/SPIRV-Cross-Vulnerable
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SPIRV-Cross-Vulnerable/reference
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Hans-Kristian Arntzen d6b29ab017 HLSL: Rewrite how block IO is emitted. 
Emit block members directly in the IO structs and sort them.
Ensures we can get some kind of stable order between stages.

To complete the story, we'll need to be able to inject unused inputs /
builtins, or eliminate unused outputs (probably easiest solution).
2021-06-28 15:04:49 +02:00
..
opt HLSL: Rewrite how block IO is emitted. 2021-06-28 15:04:49 +02:00
shaders Handle SPIR-V 1.4 selection constructs. 2021-06-28 12:23:44 +02:00
shaders-hlsl HLSL: Rewrite how block IO is emitted. 2021-06-28 15:04:49 +02:00
shaders-hlsl-no-opt HLSL: Rewrite how block IO is emitted. 2021-06-28 15:04:49 +02:00
shaders-msl Handle SPIR-V 1.4 selection constructs. 2021-06-28 12:23:44 +02:00
shaders-msl-no-opt Handle SPIR-V 1.4 selection constructs. 2021-06-28 12:23:44 +02:00
shaders-no-opt Handle SPIR-V 1.4 selection constructs. 2021-06-28 12:23:44 +02:00
shaders-reflection Parser: Don't assume OpTypePointer will always take a SPIRType. 2020-11-03 10:53:37 +01:00
shaders-ue4/asm Handle SPIR-V 1.4 selection constructs. 2021-06-28 12:23:44 +02:00
shaders-ue4-no-opt/asm Implement context-sensitive expression read tracking. 2020-06-29 12:20:35 +02:00