GLSL: Support KHR_subgroup_arithmetic IMul/FMul
Support NV workarounds for IMul/FMul Reduce/InclusiveScan/ExclusiveScan
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georgeouzou
parent
ab3a6212b8
commit
168e9f2cc9
155
spirv_glsl.cpp
155
spirv_glsl.cpp
@ -4050,10 +4050,48 @@ void CompilerGLSL::emit_subgroup_arithmetic_workaround(std::string func, Op op,
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break;
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}
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case OpGroupNonUniformIMul:
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{
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type_infos.emplace_back(TypeInfo{ "uint", "1u" });
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type_infos.emplace_back(TypeInfo{ "uvec2", "uvec2(1u)" });
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type_infos.emplace_back(TypeInfo{ "uvec3", "uvec3(1u)" });
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type_infos.emplace_back(TypeInfo{ "uvec4", "uvec4(1u)" });
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type_infos.emplace_back(TypeInfo{ "int", "1" });
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type_infos.emplace_back(TypeInfo{ "ivec2", "ivec2(1)" });
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type_infos.emplace_back(TypeInfo{ "ivec3", "ivec3(1)" });
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type_infos.emplace_back(TypeInfo{ "ivec4", "ivec4(1)" });
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break;
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}
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case OpGroupNonUniformFMul:
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{
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type_infos.emplace_back(TypeInfo{ "float", "1.0f" });
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type_infos.emplace_back(TypeInfo{ "vec2", "vec2(1.0f)" });
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type_infos.emplace_back(TypeInfo{ "vec3", "vec3(1.0f)" });
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type_infos.emplace_back(TypeInfo{ "vec4", "vec4(1.0f)" });
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type_infos.emplace_back(TypeInfo{ "double", "0.0LF" });
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type_infos.emplace_back(TypeInfo{ "dvec2", "dvec2(1.0LF)" });
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type_infos.emplace_back(TypeInfo{ "dvec3", "dvec3(1.0LF)" });
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type_infos.emplace_back(TypeInfo{ "dvec4", "dvec4(1.0LF)" });
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break;
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}
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default:
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SPIRV_CROSS_THROW("Unsupported workaround for arithmetic group operation");
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}
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const bool op_is_addition = op == OpGroupNonUniformIAdd || op == OpGroupNonUniformFAdd;
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const bool op_is_multiplication = op == OpGroupNonUniformIMul || op == OpGroupNonUniformFMul;
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std::string op_symbol;
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if (op_is_addition)
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{
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op_symbol = "+=";
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}
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else if (op_is_multiplication)
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{
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op_symbol = "*=";
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}
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for (const TypeInfo& t : type_infos) {
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statement(t.type, " ", func, "(", t.type, " v)");
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begin_scope();
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@ -4065,15 +4103,18 @@ void CompilerGLSL::emit_subgroup_arithmetic_workaround(std::string func, Op op,
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statement(result, " = v;");
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statement("for (uint i = 1u; i <= total; i <<= 1u)");
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begin_scope();
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statement("bool valid;");
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if (group_op == GroupOperationReduce)
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{
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statement(result, " += shuffleXorNV(", result, ", i, gl_SubgroupSize);");
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statement(t.type, " s = shuffleXorNV(", result, ", i, gl_SubgroupSize, valid);");
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}
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else if (group_op == GroupOperationExclusiveScan || group_op == GroupOperationInclusiveScan)
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{
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statement("bool valid;");
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statement(t.type, " s = shuffleUpNV(", result, ", i, gl_SubgroupSize, valid);");
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statement(result, " += valid ? s : ", t.identity, ";");
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}
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if (op_is_addition || op_is_multiplication)
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{
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statement(result, " ", op_symbol, " valid ? s : ", t.identity, ";");
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}
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end_scope();
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if (group_op == GroupOperationExclusiveScan)
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@ -4103,7 +4144,10 @@ void CompilerGLSL::emit_subgroup_arithmetic_workaround(std::string func, Op op,
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{
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statement("valid = valid && (i < total);");
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}
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statement(result, " += valid ? s : ", t.identity, ";");
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if (op_is_addition || op_is_multiplication)
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{
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statement(result, " ", op_symbol, " valid ? s : ", t.identity, ";");
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}
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end_scope();
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end_scope();
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statement("return ", result, ";");
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@ -4552,6 +4596,19 @@ void CompilerGLSL::emit_extension_workarounds(spv::ExecutionModel model)
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OpGroupNonUniformFAdd, GroupOperationExclusiveScan);
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arithmetic_feature_helper(Supp::SubgroupArithmeticFAddInclusiveScan, "subgroupInclusiveAdd",
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OpGroupNonUniformFAdd, GroupOperationInclusiveScan);
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arithmetic_feature_helper(Supp::SubgroupArithmeticIMulReduce, "subgroupMul", OpGroupNonUniformIMul,
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GroupOperationReduce);
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arithmetic_feature_helper(Supp::SubgroupArithmeticIMulExclusiveScan, "subgroupExclusiveMul",
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OpGroupNonUniformIMul, GroupOperationExclusiveScan);
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arithmetic_feature_helper(Supp::SubgroupArithmeticIMulInclusiveScan, "subgroupInclusiveMul",
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OpGroupNonUniformIMul, GroupOperationInclusiveScan);
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arithmetic_feature_helper(Supp::SubgroupArithmeticFMulReduce, "subgroupMul", OpGroupNonUniformFMul,
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GroupOperationReduce);
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arithmetic_feature_helper(Supp::SubgroupArithmeticFMulExclusiveScan, "subgroupExclusiveMul",
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OpGroupNonUniformFMul, GroupOperationExclusiveScan);
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arithmetic_feature_helper(Supp::SubgroupArithmeticFMulInclusiveScan, "subgroupInclusiveMul",
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OpGroupNonUniformFMul, GroupOperationInclusiveScan);
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}
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if (!workaround_ubo_load_overload_types.empty())
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@ -7273,6 +7330,8 @@ bool CompilerGLSL::is_supported_subgroup_op_in_opengl(spv::Op op, const uint32_t
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return true;
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case OpGroupNonUniformIAdd:
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case OpGroupNonUniformFAdd:
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case OpGroupNonUniformIMul:
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case OpGroupNonUniformFMul:
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{
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const GroupOperation operation = static_cast<GroupOperation>(ops[3]);
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if (operation == GroupOperationReduce || operation == GroupOperationInclusiveScan ||
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@ -8946,58 +9005,34 @@ void CompilerGLSL::emit_subgroup_op(const Instruction &i)
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}
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break;
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case OpGroupNonUniformIAdd:
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{
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auto operation = static_cast<GroupOperation>(ops[3]);
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if (operation == GroupOperationClusteredReduce)
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{
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require_extension_internal("GL_KHR_shader_subgroup_clustered");
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}
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else if (operation == GroupOperationReduce)
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{
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmeticIAddReduce);
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}
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else if (operation == GroupOperationExclusiveScan)
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{
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmeticIAddExclusiveScan);
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}
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else if (operation == GroupOperationInclusiveScan)
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{
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmeticIAddInclusiveScan);
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}
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else
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SPIRV_CROSS_THROW("Invalid group operation.");
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break;
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// clang-format off
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#define GLSL_GROUP_OP(OP)\
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case OpGroupNonUniform##OP:\
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{\
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auto operation = static_cast<GroupOperation>(ops[3]);\
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if (operation == GroupOperationClusteredReduce)\
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require_extension_internal("GL_KHR_shader_subgroup_clustered");\
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else if (operation == GroupOperationReduce)\
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmetic##OP##Reduce);\
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else if (operation == GroupOperationExclusiveScan)\
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmetic##OP##ExclusiveScan);\
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else if (operation == GroupOperationInclusiveScan)\
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmetic##OP##InclusiveScan);\
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else\
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SPIRV_CROSS_THROW("Invalid group operation.");\
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break;\
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}
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case OpGroupNonUniformFAdd:
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{
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auto operation = static_cast<GroupOperation>(ops[3]);
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if (operation == GroupOperationClusteredReduce)
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{
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require_extension_internal("GL_KHR_shader_subgroup_clustered");
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}
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else if (operation == GroupOperationReduce)
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{
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmeticFAddReduce);
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}
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else if (operation == GroupOperationExclusiveScan)
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{
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmeticFAddExclusiveScan);
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}
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else if (operation == GroupOperationInclusiveScan)
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{
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request_subgroup_feature(ShaderSubgroupSupportHelper::SubgroupArithmeticFAddInclusiveScan);
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}
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else
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SPIRV_CROSS_THROW("Invalid group operation.");
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break;
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}
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GLSL_GROUP_OP(IAdd)
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GLSL_GROUP_OP(FAdd)
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GLSL_GROUP_OP(IMul)
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GLSL_GROUP_OP(FMul)
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#undef GLSL_GROUP_OP
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// clang-format on
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case OpGroupNonUniformFMul:
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case OpGroupNonUniformFMin:
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case OpGroupNonUniformFMax:
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case OpGroupNonUniformIMul:
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case OpGroupNonUniformSMin:
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case OpGroupNonUniformSMax:
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case OpGroupNonUniformUMin:
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@ -17916,9 +17951,15 @@ CompilerGLSL::ShaderSubgroupSupportHelper::FeatureVector CompilerGLSL::ShaderSub
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case SubgroupArithmeticIAddInclusiveScan:
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case SubgroupArithmeticFAddReduce:
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case SubgroupArithmeticFAddInclusiveScan:
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case SubgroupArithmeticIMulReduce:
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case SubgroupArithmeticIMulInclusiveScan:
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case SubgroupArithmeticFMulReduce:
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case SubgroupArithmeticFMulInclusiveScan:
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return { SubgroupSize, SubgroupBallot, SubgroupBallotBitCount, SubgroupMask, SubgroupBallotBitExtract };
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case SubgroupArithmeticIAddExclusiveScan:
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case SubgroupArithmeticFAddExclusiveScan:
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case SubgroupArithmeticIMulExclusiveScan:
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case SubgroupArithmeticFMulExclusiveScan:
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return { SubgroupSize, SubgroupBallot, SubgroupBallotBitCount,
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SubgroupMask, SubgroupElect, SubgroupBallotBitExtract };
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default:
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@ -17939,7 +17980,9 @@ bool CompilerGLSL::ShaderSubgroupSupportHelper::can_feature_be_implemented_witho
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true, // SubgroupBalloFindLSB_MSB
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false, false, false, false,
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true, // SubgroupMemBarrier - replaced with workgroup memory barriers
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false, false, true, false, false, false, false, false, false, false
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false, false, true, false,
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false, false, false, false, false, false, // iadd, fadd
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false, false, false, false, false, false, // imul , fmul
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};
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return retval[feature];
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@ -17955,6 +17998,8 @@ CompilerGLSL::ShaderSubgroupSupportHelper::Candidate CompilerGLSL::ShaderSubgrou
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KHR_shader_subgroup_ballot, KHR_shader_subgroup_ballot, KHR_shader_subgroup_ballot, KHR_shader_subgroup_ballot,
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KHR_shader_subgroup_arithmetic, KHR_shader_subgroup_arithmetic, KHR_shader_subgroup_arithmetic,
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KHR_shader_subgroup_arithmetic, KHR_shader_subgroup_arithmetic, KHR_shader_subgroup_arithmetic,
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KHR_shader_subgroup_arithmetic, KHR_shader_subgroup_arithmetic, KHR_shader_subgroup_arithmetic,
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KHR_shader_subgroup_arithmetic, KHR_shader_subgroup_arithmetic, KHR_shader_subgroup_arithmetic,
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};
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return extensions[feature];
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@ -18056,6 +18101,12 @@ CompilerGLSL::ShaderSubgroupSupportHelper::CandidateVector CompilerGLSL::ShaderS
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case SubgroupArithmeticFAddReduce:
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case SubgroupArithmeticFAddExclusiveScan:
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case SubgroupArithmeticFAddInclusiveScan:
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case SubgroupArithmeticIMulReduce:
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case SubgroupArithmeticIMulExclusiveScan:
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case SubgroupArithmeticIMulInclusiveScan:
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case SubgroupArithmeticFMulReduce:
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case SubgroupArithmeticFMulExclusiveScan:
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case SubgroupArithmeticFMulInclusiveScan:
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return { KHR_shader_subgroup_arithmetic, NV_shader_thread_shuffle };
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default:
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return {};
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@ -331,6 +331,12 @@ protected:
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SubgroupArithmeticFAddReduce = 19,
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SubgroupArithmeticFAddExclusiveScan = 20,
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SubgroupArithmeticFAddInclusiveScan = 21,
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SubgroupArithmeticIMulReduce = 22,
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SubgroupArithmeticIMulExclusiveScan = 23,
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SubgroupArithmeticIMulInclusiveScan = 24,
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SubgroupArithmeticFMulReduce = 25,
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SubgroupArithmeticFMulExclusiveScan = 26,
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SubgroupArithmeticFMulInclusiveScan = 27,
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FeatureCount
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};
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