f1b411c9e8
This is somewhat awkward to support, but the best effort we can do here is to analyze various Load/Store opcodes and deduce the ideal overall alignment based on this. This is not a 100% perfect solution, but should be correct for any reasonable use case. Also fix various nitpicks with BDA support while I'm at it.
36 lines
834 B
Plaintext
36 lines
834 B
Plaintext
#version 450
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#extension GL_EXT_buffer_reference : require
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layout(local_size_x = 64, local_size_y = 1, local_size_z = 1) in;
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layout(buffer_reference) buffer RO;
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layout(buffer_reference) buffer RW;
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layout(buffer_reference) buffer WO;
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layout(buffer_reference, buffer_reference_align = 16, std430) readonly buffer RO
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{
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vec4 v[];
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};
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layout(buffer_reference, buffer_reference_align = 16, std430) restrict buffer RW
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{
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vec4 v[];
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};
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layout(buffer_reference, buffer_reference_align = 16, std430) coherent writeonly buffer WO
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{
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vec4 v[];
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};
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layout(push_constant, std430) uniform Registers
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{
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RO ro;
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RW rw;
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WO wo;
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} registers;
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void main()
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{
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registers.rw.v[gl_GlobalInvocationID.x] = registers.ro.v[gl_GlobalInvocationID.x];
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registers.wo.v[gl_GlobalInvocationID.x] = registers.ro.v[gl_GlobalInvocationID.x];
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}
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