SPIRV-Cross/shaders-msl-no-opt/asm
2022-01-18 12:39:16 +01:00
..
comp Test aliased names in declared LUTs. 2022-01-18 12:39:16 +01:00
frag Handle Modf/Frexp in more cases. 2021-11-07 11:36:44 +01:00
masking MSL: Emit multiple threadgroup slices for multi-patch. 2021-04-19 12:10:49 +02:00
packing MSL: Support edge case with DX layout in scalar block layout. 2020-04-20 15:29:24 +02:00
tesc Handle edge cases in OpCopyMemory. 2021-03-08 14:15:27 +01:00
tese MSL: Improve handling of split tessellation access chains. 2021-05-21 16:32:03 +02:00
vert MSL: Deal with pointer-to-pointer qualifier ordering. 2021-02-26 13:37:14 +01:00
temporary.zero-initialize.asm.frag Add support for forcefully zero-initialized variables. 2020-03-26 13:38:27 +01:00