SPIRV-Cross/reference/shaders-msl-no-opt
Hans-Kristian Arntzen 46c48ee6b5 MSL: Rewrite how IO blocks are emitted in multi-patch mode.
Firstly, never flatten inputs or outputs in multi-patch mode.
The main scenario where we do need to care is Block IO.
In this case, we should only flatten the top-level member, and after
that we use access chains as normal.

Using structs in Input storage class is now possible as well. We don't
need to consider per-location fixups at all here. In Vulkan, IO structs
must match exactly. Only plain vectors can have smaller vector sizes as
a special case.
2021-04-19 12:10:49 +02:00
..
asm MSL: Rewrite how IO blocks are emitted in multi-patch mode. 2021-04-19 12:10:49 +02:00
comp MSL: Add test for logical subgroup arith ops. 2021-03-08 12:57:37 +01:00
components MSL: Deal with padded fragment output + Component decoration. 2020-01-07 17:02:12 +01:00
frag Deal better with CompositeExtract from constant composite. 2021-01-22 12:30:16 +01:00
packing MSL: Do not emit swizzled writes in packing fixups. 2020-07-06 10:03:46 +02:00
tesc MSL: Handle load and store to TessLevel array in TESC. 2021-02-17 13:26:08 +01:00
tese MSL: Sort builtin IO block members by builtin type. 2021-04-19 12:10:49 +02:00
vert MSL: Always enable Outputs in vertex stages. 2021-01-07 11:24:47 +01:00
vulkan/frag Deal better with CompositeExtract from constant composite. 2021-01-22 12:30:16 +01:00