2016-01-07 18:44:22 +00:00
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// Copyright (c) 2015-2016 The Khronos Group Inc.
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2015-05-22 17:26:19 +00:00
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//
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2016-09-01 19:33:59 +00:00
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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2015-05-22 17:26:19 +00:00
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//
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2016-09-01 19:33:59 +00:00
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// http://www.apache.org/licenses/LICENSE-2.0
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2015-05-22 17:26:19 +00:00
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//
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2016-09-01 19:33:59 +00:00
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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2015-05-22 17:26:19 +00:00
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2015-10-27 20:27:05 +00:00
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#ifndef LIBSPIRV_OPERAND_H_
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#define LIBSPIRV_OPERAND_H_
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2015-05-22 17:26:19 +00:00
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Use opcode operand definitions from SPIR-V specification generator.
The assembler and disassembler now use a dynamically adjusted
sequence of expected operand types. (Internally, it is a deque,
for readability.) Both parsers repeatedly pull an expected operand
type from the left of this pattern list, and try to match the next
input token against it.
The expected pattern is adjusted during the parse to accommodate:
- an extended instruction's expected operands, depending on the
extended instruction's index.
- when an operand itself has operands
- to handle sequences of zero or more operands, or pairs of
operands. These are expanded lazily during the parse.
Adds spv::OperandClass from the SPIR-V specification generator.
Modifies spv_operand_desc_t:
- adds hasResult, hasType, and operandClass array to the opcode
description type.
- "wordCount" is replaced with "numTypes", which counts the number
of entries in operandTypes. And each of those describes a
*logical* operand, including the type id for the instruction,
and the result id for the instruction. A logical operand could be
variable-width, such as a literal string.
Adds opcode.inc, an automatically-generated table of operation
descriptions, with one line to describe each core instruction.
Externally, we have modified the SPIR-V spec doc generator to
emit this file.
(We have hacked this copy to use the old semantics for OpLine.)
Inside the assembler, parsing an operand may fail with new
error code SPV_FAIL_MATCH. For an optional operand, this is not
fatal, but should trigger backtracking at a higher level.
The spvTextIsStartOfNewInst checks the case of the third letter
of what might be an opcode. So now, "OpenCL" does not look like
an opcode name.
In assembly, the EntryPoint name field is mandatory, but can be
an empty string.
Adjust tests for changes to:
- OpSampedImage
- OpTypeSampler
2015-08-27 17:03:52 +00:00
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#include <deque>
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2017-08-09 18:01:12 +00:00
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#include <functional>
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Use opcode operand definitions from SPIR-V specification generator.
The assembler and disassembler now use a dynamically adjusted
sequence of expected operand types. (Internally, it is a deque,
for readability.) Both parsers repeatedly pull an expected operand
type from the left of this pattern list, and try to match the next
input token against it.
The expected pattern is adjusted during the parse to accommodate:
- an extended instruction's expected operands, depending on the
extended instruction's index.
- when an operand itself has operands
- to handle sequences of zero or more operands, or pairs of
operands. These are expanded lazily during the parse.
Adds spv::OperandClass from the SPIR-V specification generator.
Modifies spv_operand_desc_t:
- adds hasResult, hasType, and operandClass array to the opcode
description type.
- "wordCount" is replaced with "numTypes", which counts the number
of entries in operandTypes. And each of those describes a
*logical* operand, including the type id for the instruction,
and the result id for the instruction. A logical operand could be
variable-width, such as a literal string.
Adds opcode.inc, an automatically-generated table of operation
descriptions, with one line to describe each core instruction.
Externally, we have modified the SPIR-V spec doc generator to
emit this file.
(We have hacked this copy to use the old semantics for OpLine.)
Inside the assembler, parsing an operand may fail with new
error code SPV_FAIL_MATCH. For an optional operand, this is not
fatal, but should trigger backtracking at a higher level.
The spvTextIsStartOfNewInst checks the case of the third letter
of what might be an opcode. So now, "OpenCL" does not look like
an opcode name.
In assembly, the EntryPoint name field is mandatory, but can be
an empty string.
Adjust tests for changes to:
- OpSampedImage
- OpTypeSampler
2015-08-27 17:03:52 +00:00
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2016-02-17 19:44:00 +00:00
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#include "spirv-tools/libspirv.h"
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2015-11-11 17:40:25 +00:00
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#include "table.h"
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2015-05-22 17:26:19 +00:00
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2015-11-16 15:48:43 +00:00
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// A sequence of operand types.
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//
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// A SPIR-V parser uses an operand pattern to describe what is expected
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// next on the input.
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//
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// As we parse an instruction in text or binary form from left to right,
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2017-06-27 23:28:22 +00:00
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// we pop and push at the end of the pattern vector. Symbols later in the
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// pattern vector are matched against the input before symbols earlier in the
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// pattern vector are matched.
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// Using a vector in this way reduces memory traffic, which is good for
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// performance.
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using spv_operand_pattern_t = std::vector<spv_operand_type_t>;
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Use opcode operand definitions from SPIR-V specification generator.
The assembler and disassembler now use a dynamically adjusted
sequence of expected operand types. (Internally, it is a deque,
for readability.) Both parsers repeatedly pull an expected operand
type from the left of this pattern list, and try to match the next
input token against it.
The expected pattern is adjusted during the parse to accommodate:
- an extended instruction's expected operands, depending on the
extended instruction's index.
- when an operand itself has operands
- to handle sequences of zero or more operands, or pairs of
operands. These are expanded lazily during the parse.
Adds spv::OperandClass from the SPIR-V specification generator.
Modifies spv_operand_desc_t:
- adds hasResult, hasType, and operandClass array to the opcode
description type.
- "wordCount" is replaced with "numTypes", which counts the number
of entries in operandTypes. And each of those describes a
*logical* operand, including the type id for the instruction,
and the result id for the instruction. A logical operand could be
variable-width, such as a literal string.
Adds opcode.inc, an automatically-generated table of operation
descriptions, with one line to describe each core instruction.
Externally, we have modified the SPIR-V spec doc generator to
emit this file.
(We have hacked this copy to use the old semantics for OpLine.)
Inside the assembler, parsing an operand may fail with new
error code SPV_FAIL_MATCH. For an optional operand, this is not
fatal, but should trigger backtracking at a higher level.
The spvTextIsStartOfNewInst checks the case of the third letter
of what might be an opcode. So now, "OpenCL" does not look like
an opcode name.
In assembly, the EntryPoint name field is mandatory, but can be
an empty string.
Adjust tests for changes to:
- OpSampedImage
- OpTypeSampler
2015-08-27 17:03:52 +00:00
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2015-11-16 15:48:43 +00:00
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// Finds the named operand in the table. The type parameter specifies the
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// operand's group. A handle of the operand table entry for this operand will
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// be written into *entry.
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2018-03-14 17:06:18 +00:00
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spv_result_t spvOperandTableNameLookup(spv_target_env,
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const spv_operand_table table,
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2015-05-22 17:26:19 +00:00
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const spv_operand_type_t type,
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2015-09-29 14:56:32 +00:00
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const char* name,
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2015-11-16 15:48:43 +00:00
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const size_t name_length,
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spv_operand_desc* entry);
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2015-05-22 17:26:19 +00:00
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2015-11-16 15:48:43 +00:00
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// Finds the operand with value in the table. The type parameter specifies the
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// operand's group. A handle of the operand table entry for this operand will
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// be written into *entry.
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2018-03-14 17:06:18 +00:00
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spv_result_t spvOperandTableValueLookup(spv_target_env,
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const spv_operand_table table,
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2015-05-22 17:26:19 +00:00
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const spv_operand_type_t type,
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const uint32_t value,
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2015-11-16 15:48:43 +00:00
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spv_operand_desc* entry);
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2015-05-22 17:26:19 +00:00
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2015-11-16 15:48:43 +00:00
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// Gets the name string of the non-variable operand type.
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2015-09-29 14:56:32 +00:00
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const char* spvOperandTypeStr(spv_operand_type_t type);
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2015-05-22 17:26:19 +00:00
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2017-12-03 19:26:16 +00:00
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// Returns true if the given type is concrete.
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bool spvOperandIsConcrete(spv_operand_type_t type);
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// Returns true if the given type is concrete and also a mask.
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2016-02-02 17:05:34 +00:00
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bool spvOperandIsConcreteMask(spv_operand_type_t type);
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2015-11-16 15:48:43 +00:00
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// Returns true if an operand of the given type is optional.
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Use opcode operand definitions from SPIR-V specification generator.
The assembler and disassembler now use a dynamically adjusted
sequence of expected operand types. (Internally, it is a deque,
for readability.) Both parsers repeatedly pull an expected operand
type from the left of this pattern list, and try to match the next
input token against it.
The expected pattern is adjusted during the parse to accommodate:
- an extended instruction's expected operands, depending on the
extended instruction's index.
- when an operand itself has operands
- to handle sequences of zero or more operands, or pairs of
operands. These are expanded lazily during the parse.
Adds spv::OperandClass from the SPIR-V specification generator.
Modifies spv_operand_desc_t:
- adds hasResult, hasType, and operandClass array to the opcode
description type.
- "wordCount" is replaced with "numTypes", which counts the number
of entries in operandTypes. And each of those describes a
*logical* operand, including the type id for the instruction,
and the result id for the instruction. A logical operand could be
variable-width, such as a literal string.
Adds opcode.inc, an automatically-generated table of operation
descriptions, with one line to describe each core instruction.
Externally, we have modified the SPIR-V spec doc generator to
emit this file.
(We have hacked this copy to use the old semantics for OpLine.)
Inside the assembler, parsing an operand may fail with new
error code SPV_FAIL_MATCH. For an optional operand, this is not
fatal, but should trigger backtracking at a higher level.
The spvTextIsStartOfNewInst checks the case of the third letter
of what might be an opcode. So now, "OpenCL" does not look like
an opcode name.
In assembly, the EntryPoint name field is mandatory, but can be
an empty string.
Adjust tests for changes to:
- OpSampedImage
- OpTypeSampler
2015-08-27 17:03:52 +00:00
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bool spvOperandIsOptional(spv_operand_type_t type);
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2015-11-16 15:48:43 +00:00
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// Returns true if an operand type represents zero or more logical operands.
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//
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// Note that a single logical operand may still be a variable number of words.
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// For example, a literal string may be many words, but is just one logical
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// operand.
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Use opcode operand definitions from SPIR-V specification generator.
The assembler and disassembler now use a dynamically adjusted
sequence of expected operand types. (Internally, it is a deque,
for readability.) Both parsers repeatedly pull an expected operand
type from the left of this pattern list, and try to match the next
input token against it.
The expected pattern is adjusted during the parse to accommodate:
- an extended instruction's expected operands, depending on the
extended instruction's index.
- when an operand itself has operands
- to handle sequences of zero or more operands, or pairs of
operands. These are expanded lazily during the parse.
Adds spv::OperandClass from the SPIR-V specification generator.
Modifies spv_operand_desc_t:
- adds hasResult, hasType, and operandClass array to the opcode
description type.
- "wordCount" is replaced with "numTypes", which counts the number
of entries in operandTypes. And each of those describes a
*logical* operand, including the type id for the instruction,
and the result id for the instruction. A logical operand could be
variable-width, such as a literal string.
Adds opcode.inc, an automatically-generated table of operation
descriptions, with one line to describe each core instruction.
Externally, we have modified the SPIR-V spec doc generator to
emit this file.
(We have hacked this copy to use the old semantics for OpLine.)
Inside the assembler, parsing an operand may fail with new
error code SPV_FAIL_MATCH. For an optional operand, this is not
fatal, but should trigger backtracking at a higher level.
The spvTextIsStartOfNewInst checks the case of the third letter
of what might be an opcode. So now, "OpenCL" does not look like
an opcode name.
In assembly, the EntryPoint name field is mandatory, but can be
an empty string.
Adjust tests for changes to:
- OpSampedImage
- OpTypeSampler
2015-08-27 17:03:52 +00:00
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bool spvOperandIsVariable(spv_operand_type_t type);
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2017-06-27 23:28:22 +00:00
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// Append a list of operand types to the end of the pattern vector.
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2015-11-16 15:48:43 +00:00
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// The types parameter specifies the source array of types, ending with
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// SPV_OPERAND_TYPE_NONE.
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2017-06-27 23:28:22 +00:00
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void spvPushOperandTypes(const spv_operand_type_t* types,
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spv_operand_pattern_t* pattern);
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Use opcode operand definitions from SPIR-V specification generator.
The assembler and disassembler now use a dynamically adjusted
sequence of expected operand types. (Internally, it is a deque,
for readability.) Both parsers repeatedly pull an expected operand
type from the left of this pattern list, and try to match the next
input token against it.
The expected pattern is adjusted during the parse to accommodate:
- an extended instruction's expected operands, depending on the
extended instruction's index.
- when an operand itself has operands
- to handle sequences of zero or more operands, or pairs of
operands. These are expanded lazily during the parse.
Adds spv::OperandClass from the SPIR-V specification generator.
Modifies spv_operand_desc_t:
- adds hasResult, hasType, and operandClass array to the opcode
description type.
- "wordCount" is replaced with "numTypes", which counts the number
of entries in operandTypes. And each of those describes a
*logical* operand, including the type id for the instruction,
and the result id for the instruction. A logical operand could be
variable-width, such as a literal string.
Adds opcode.inc, an automatically-generated table of operation
descriptions, with one line to describe each core instruction.
Externally, we have modified the SPIR-V spec doc generator to
emit this file.
(We have hacked this copy to use the old semantics for OpLine.)
Inside the assembler, parsing an operand may fail with new
error code SPV_FAIL_MATCH. For an optional operand, this is not
fatal, but should trigger backtracking at a higher level.
The spvTextIsStartOfNewInst checks the case of the third letter
of what might be an opcode. So now, "OpenCL" does not look like
an opcode name.
In assembly, the EntryPoint name field is mandatory, but can be
an empty string.
Adjust tests for changes to:
- OpSampedImage
- OpTypeSampler
2015-08-27 17:03:52 +00:00
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2017-06-27 23:28:22 +00:00
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// Appends the operands expected after the given typed mask onto the
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// end of the given pattern.
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2015-11-16 15:48:43 +00:00
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//
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// Each set bit in the mask represents zero or more operand types that should
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2017-06-27 23:28:22 +00:00
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// be appended onto the pattern. Operands for a less significant bit always
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// appear after operands for a more significant bit.
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2015-11-16 15:48:43 +00:00
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//
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// If a set bit is unknown, then we assume it has no operands.
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2018-03-14 17:06:18 +00:00
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void spvPushOperandTypesForMask(spv_target_env,
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const spv_operand_table operand_table,
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2017-06-27 23:28:22 +00:00
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const spv_operand_type_t mask_type,
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const uint32_t mask,
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spv_operand_pattern_t* pattern);
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2015-09-17 21:06:10 +00:00
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2015-11-16 15:48:43 +00:00
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// Expands an operand type representing zero or more logical operands,
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// exactly once.
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//
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// If the given type represents potentially several logical operands,
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// then prepend the given pattern with the first expansion of the logical
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// operands, followed by original type. Otherwise, don't modify the pattern.
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//
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// For example, the SPV_OPERAND_TYPE_VARIABLE_ID represents zero or more
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// IDs. In that case we would prepend the pattern with SPV_OPERAND_TYPE_ID
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// followed by SPV_OPERAND_TYPE_VARIABLE_ID again.
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//
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// This also applies to zero or more tuples of logical operands. In that case
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// we prepend pattern with for the members of the tuple, followed by the
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// original type argument. The pattern must encode the fact that if any part
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// of the tuple is present, then all tuple members should be. So the first
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// member of the tuple must be optional, and the remaining members
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// non-optional.
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//
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// Returns true if we modified the pattern.
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Use opcode operand definitions from SPIR-V specification generator.
The assembler and disassembler now use a dynamically adjusted
sequence of expected operand types. (Internally, it is a deque,
for readability.) Both parsers repeatedly pull an expected operand
type from the left of this pattern list, and try to match the next
input token against it.
The expected pattern is adjusted during the parse to accommodate:
- an extended instruction's expected operands, depending on the
extended instruction's index.
- when an operand itself has operands
- to handle sequences of zero or more operands, or pairs of
operands. These are expanded lazily during the parse.
Adds spv::OperandClass from the SPIR-V specification generator.
Modifies spv_operand_desc_t:
- adds hasResult, hasType, and operandClass array to the opcode
description type.
- "wordCount" is replaced with "numTypes", which counts the number
of entries in operandTypes. And each of those describes a
*logical* operand, including the type id for the instruction,
and the result id for the instruction. A logical operand could be
variable-width, such as a literal string.
Adds opcode.inc, an automatically-generated table of operation
descriptions, with one line to describe each core instruction.
Externally, we have modified the SPIR-V spec doc generator to
emit this file.
(We have hacked this copy to use the old semantics for OpLine.)
Inside the assembler, parsing an operand may fail with new
error code SPV_FAIL_MATCH. For an optional operand, this is not
fatal, but should trigger backtracking at a higher level.
The spvTextIsStartOfNewInst checks the case of the third letter
of what might be an opcode. So now, "OpenCL" does not look like
an opcode name.
In assembly, the EntryPoint name field is mandatory, but can be
an empty string.
Adjust tests for changes to:
- OpSampedImage
- OpTypeSampler
2015-08-27 17:03:52 +00:00
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bool spvExpandOperandSequenceOnce(spv_operand_type_t type,
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spv_operand_pattern_t* pattern);
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2015-11-16 15:48:43 +00:00
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// Expands the first element in the pattern until it is a matchable operand
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// type, then pops it off the front and returns it. The pattern must not be
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// empty.
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//
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// A matchable operand type is anything other than a zero-or-more-items
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// operand type.
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Use opcode operand definitions from SPIR-V specification generator.
The assembler and disassembler now use a dynamically adjusted
sequence of expected operand types. (Internally, it is a deque,
for readability.) Both parsers repeatedly pull an expected operand
type from the left of this pattern list, and try to match the next
input token against it.
The expected pattern is adjusted during the parse to accommodate:
- an extended instruction's expected operands, depending on the
extended instruction's index.
- when an operand itself has operands
- to handle sequences of zero or more operands, or pairs of
operands. These are expanded lazily during the parse.
Adds spv::OperandClass from the SPIR-V specification generator.
Modifies spv_operand_desc_t:
- adds hasResult, hasType, and operandClass array to the opcode
description type.
- "wordCount" is replaced with "numTypes", which counts the number
of entries in operandTypes. And each of those describes a
*logical* operand, including the type id for the instruction,
and the result id for the instruction. A logical operand could be
variable-width, such as a literal string.
Adds opcode.inc, an automatically-generated table of operation
descriptions, with one line to describe each core instruction.
Externally, we have modified the SPIR-V spec doc generator to
emit this file.
(We have hacked this copy to use the old semantics for OpLine.)
Inside the assembler, parsing an operand may fail with new
error code SPV_FAIL_MATCH. For an optional operand, this is not
fatal, but should trigger backtracking at a higher level.
The spvTextIsStartOfNewInst checks the case of the third letter
of what might be an opcode. So now, "OpenCL" does not look like
an opcode name.
In assembly, the EntryPoint name field is mandatory, but can be
an empty string.
Adjust tests for changes to:
- OpSampedImage
- OpTypeSampler
2015-08-27 17:03:52 +00:00
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spv_operand_type_t spvTakeFirstMatchableOperand(spv_operand_pattern_t* pattern);
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2015-11-16 15:48:43 +00:00
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// Calculates the corresponding post-immediate alternate pattern, which allows
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// a limited set of operand types.
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2015-09-29 14:38:18 +00:00
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spv_operand_pattern_t spvAlternatePatternFollowingImmediate(
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const spv_operand_pattern_t& pattern);
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2015-09-28 21:04:39 +00:00
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2016-01-15 16:25:11 +00:00
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// Is the operand an ID?
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bool spvIsIdType(spv_operand_type_t type);
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2017-08-09 18:01:12 +00:00
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// Takes the opcode of an instruction and returns
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// a function object that will return true if the index
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// of the operand can be forward declared. This function will
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// used in the SSA validation stage of the pipeline
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std::function<bool(unsigned)> spvOperandCanBeForwardDeclaredFunction(
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SpvOp opcode);
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2015-10-27 20:27:05 +00:00
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#endif // LIBSPIRV_OPERAND_H_
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