AuroraMiddleware/SPIRV-Tools
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5bf88fcc95
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3 Commits

Author SHA1 Message Date
David Neto
5bf88fcc95 Assembler: mask expressions where 1 bits imply operands 
Properly support a memory access mask with a combination
of bits, including the Aligned bit. When the Aligned bit is
set, the parser should expect an alignment value literal operand.
 2015-10-26 12:55:33 -04:00
David Neto
5494dd4334 Assembler test for Storage Class enum values 
This covers the storage classes in SPIR-V Rev31.  Rev32 has more.
 2015-10-26 12:55:33 -04:00
David Neto
4a29131dcd Assembler test for single-valued Memory Access flag. 2015-10-26 12:55:33 -04:00