mirror of
https://github.com/KhronosGroup/SPIRV-Tools
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e8ce4355ae
This PR implements part of the add bit instruction synonym transformation. For now, the implementation covers the OpBitwiseOr, OpBitwiseXor and OpBitwiseAnd cases.
229 lines
9.2 KiB
C++
229 lines
9.2 KiB
C++
// Copyright (c) 2020 André Perez Maselco
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "source/fuzz/transformation_add_bit_instruction_synonym.h"
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#include "source/fuzz/fuzzer_util.h"
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#include "source/fuzz/instruction_descriptor.h"
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namespace spvtools {
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namespace fuzz {
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TransformationAddBitInstructionSynonym::TransformationAddBitInstructionSynonym(
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const spvtools::fuzz::protobufs::TransformationAddBitInstructionSynonym&
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message)
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: message_(message) {}
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TransformationAddBitInstructionSynonym::TransformationAddBitInstructionSynonym(
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const uint32_t instruction_result_id,
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const std::vector<uint32_t>& fresh_ids) {
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message_.set_instruction_result_id(instruction_result_id);
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*message_.mutable_fresh_ids() =
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google::protobuf::RepeatedField<google::protobuf::uint32>(
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fresh_ids.begin(), fresh_ids.end());
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}
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bool TransformationAddBitInstructionSynonym::IsApplicable(
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opt::IRContext* ir_context,
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const TransformationContext& transformation_context) const {
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auto instruction =
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ir_context->get_def_use_mgr()->GetDef(message_.instruction_result_id());
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// TODO(https://github.com/KhronosGroup/SPIRV-Tools/issues/3557):
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// Right now we only support certain operations. When this issue is addressed
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// the following conditional can use the function |spvOpcodeIsBit|.
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// |instruction| must be defined and must be a supported bit instruction.
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if (!instruction || (instruction->opcode() != SpvOpBitwiseOr &&
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instruction->opcode() != SpvOpBitwiseXor &&
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instruction->opcode() != SpvOpBitwiseAnd)) {
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return false;
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}
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// TODO(https://github.com/KhronosGroup/SPIRV-Tools/issues/3792):
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// Right now, only integer operands are supported.
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if (ir_context->get_type_mgr()->GetType(instruction->type_id())->AsVector()) {
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return false;
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}
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// TODO(https://github.com/KhronosGroup/SPIRV-Tools/issues/3791):
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// This condition could be relaxed if the index exists as another integer
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// type.
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// All bit indexes must be defined as 32-bit unsigned integers.
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uint32_t width = ir_context->get_type_mgr()
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->GetType(instruction->type_id())
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->AsInteger()
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->width();
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for (uint32_t i = 0; i < width; i++) {
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if (!fuzzerutil::MaybeGetIntegerConstant(ir_context, transformation_context,
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{i}, 32, false, false)) {
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return false;
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}
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}
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// |message_.fresh_ids.size| must have the exact number of fresh ids required
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// to apply the transformation.
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if (static_cast<uint32_t>(message_.fresh_ids().size()) !=
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GetRequiredFreshIdCount(ir_context, instruction)) {
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return false;
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}
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// All ids in |message_.fresh_ids| must be fresh.
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for (uint32_t fresh_id : message_.fresh_ids()) {
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if (!fuzzerutil::IsFreshId(ir_context, fresh_id)) {
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return false;
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}
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}
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return true;
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}
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void TransformationAddBitInstructionSynonym::Apply(
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opt::IRContext* ir_context,
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TransformationContext* transformation_context) const {
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auto bit_instruction =
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ir_context->get_def_use_mgr()->GetDef(message_.instruction_result_id());
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switch (bit_instruction->opcode()) {
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case SpvOpBitwiseOr:
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case SpvOpBitwiseXor:
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case SpvOpBitwiseAnd:
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AddBitwiseSynonym(ir_context, transformation_context, bit_instruction);
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break;
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default:
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assert(false && "Should be unreachable.");
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break;
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}
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ir_context->InvalidateAnalysesExceptFor(opt::IRContext::kAnalysisNone);
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}
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protobufs::Transformation TransformationAddBitInstructionSynonym::ToMessage()
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const {
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protobufs::Transformation result;
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*result.mutable_add_bit_instruction_synonym() = message_;
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return result;
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}
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uint32_t TransformationAddBitInstructionSynonym::GetRequiredFreshIdCount(
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opt::IRContext* ir_context, opt::Instruction* bit_instruction) {
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// TODO(https://github.com/KhronosGroup/SPIRV-Tools/issues/3557):
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// Right now, only certain operations are supported.
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switch (bit_instruction->opcode()) {
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case SpvOpBitwiseOr:
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case SpvOpBitwiseXor:
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case SpvOpBitwiseAnd:
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return 4 * ir_context->get_type_mgr()
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->GetType(bit_instruction->type_id())
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->AsInteger()
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->width() -
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1;
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default:
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assert(false && "Unsupported bit instruction.");
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return 0;
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}
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}
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void TransformationAddBitInstructionSynonym::AddBitwiseSynonym(
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opt::IRContext* ir_context, TransformationContext* transformation_context,
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opt::Instruction* bit_instruction) const {
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// Fresh id iterator.
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auto fresh_id = message_.fresh_ids().begin();
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// |width| is the bit width of operands (8, 16, 32 or 64).
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const uint32_t width = ir_context->get_type_mgr()
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->GetType(bit_instruction->type_id())
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->AsInteger()
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->width();
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// |count| is the number of bits to be extracted and inserted at a time.
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const uint32_t count = fuzzerutil::MaybeGetIntegerConstant(
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ir_context, *transformation_context, {1}, 32, false, false);
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// |bitwise_ids| is the collection of OpBiwise* instructions that evaluate a
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// pair of extracted bits. Those ids will be used to insert the result bits.
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std::vector<uint32_t> bitwise_ids(width);
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for (uint32_t i = 0; i < width; i++) {
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// |offset| is the current bit index.
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uint32_t offset = fuzzerutil::MaybeGetIntegerConstant(
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ir_context, *transformation_context, {i}, 32, false, false);
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// |bit_extract_ids| are the two extracted bits from the operands.
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std::vector<uint32_t> bit_extract_ids;
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// Extracts the i-th bit from operands.
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for (auto operand = bit_instruction->begin() + 2;
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operand != bit_instruction->end(); operand++) {
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auto bit_extract =
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opt::Instruction(ir_context, SpvOpBitFieldUExtract,
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bit_instruction->type_id(), *fresh_id++,
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{{SPV_OPERAND_TYPE_ID, operand->words},
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{SPV_OPERAND_TYPE_ID, {offset}},
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{SPV_OPERAND_TYPE_ID, {count}}});
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bit_instruction->InsertBefore(MakeUnique<opt::Instruction>(bit_extract));
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fuzzerutil::UpdateModuleIdBound(ir_context, bit_extract.result_id());
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bit_extract_ids.push_back(bit_extract.result_id());
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}
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// Applies |bit_instruction| to the pair of extracted bits.
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auto bitwise =
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opt::Instruction(ir_context, bit_instruction->opcode(),
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bit_instruction->type_id(), *fresh_id++,
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{{SPV_OPERAND_TYPE_ID, {bit_extract_ids[0]}},
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{SPV_OPERAND_TYPE_ID, {bit_extract_ids[1]}}});
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bit_instruction->InsertBefore(MakeUnique<opt::Instruction>(bitwise));
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fuzzerutil::UpdateModuleIdBound(ir_context, bitwise.result_id());
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bitwise_ids[i] = bitwise.result_id();
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}
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// The first two ids in |bitwise_ids| are used to insert the first two bits of
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// the result.
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uint32_t offset = fuzzerutil::MaybeGetIntegerConstant(
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ir_context, *transformation_context, {1}, 32, false, false);
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auto bit_insert = opt::Instruction(ir_context, SpvOpBitFieldInsert,
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bit_instruction->type_id(), *fresh_id++,
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{{SPV_OPERAND_TYPE_ID, {bitwise_ids[0]}},
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{SPV_OPERAND_TYPE_ID, {bitwise_ids[1]}},
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{SPV_OPERAND_TYPE_ID, {offset}},
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{SPV_OPERAND_TYPE_ID, {count}}});
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bit_instruction->InsertBefore(MakeUnique<opt::Instruction>(bit_insert));
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fuzzerutil::UpdateModuleIdBound(ir_context, bit_insert.result_id());
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// Inserts the remaining bits.
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for (uint32_t i = 2; i < width; i++) {
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offset = fuzzerutil::MaybeGetIntegerConstant(
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ir_context, *transformation_context, {i}, 32, false, false);
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bit_insert =
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opt::Instruction(ir_context, SpvOpBitFieldInsert,
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bit_instruction->type_id(), *fresh_id++,
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{{SPV_OPERAND_TYPE_ID, {bit_insert.result_id()}},
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{SPV_OPERAND_TYPE_ID, {bitwise_ids[i]}},
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{SPV_OPERAND_TYPE_ID, {offset}},
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{SPV_OPERAND_TYPE_ID, {count}}});
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bit_instruction->InsertBefore(MakeUnique<opt::Instruction>(bit_insert));
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fuzzerutil::UpdateModuleIdBound(ir_context, bit_insert.result_id());
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}
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ir_context->InvalidateAnalysesExceptFor(opt::IRContext::kAnalysisNone);
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// Adds the fact that the last |bit_insert| instruction is synonymous of
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// |bit_instruction|.
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transformation_context->GetFactManager()->AddFactDataSynonym(
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MakeDataDescriptor(bit_insert.result_id(), {}),
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MakeDataDescriptor(bit_instruction->result_id(), {}), ir_context);
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}
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} // namespace fuzz
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} // namespace spvtools
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