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https://github.com/KhronosGroup/SPIRV-Tools
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2c0ce87210
Introduce a pass that does a DCE type analysis for vector elements instead of the whole vector as a single element. It will then rewrite instructions that are not used with something else. For example, an instruction whose value are not used, even though it is referenced, is replaced with an OpUndef.
276 lines
10 KiB
C++
276 lines
10 KiB
C++
// Copyright (c) 2018 Google LLC.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "vector_dce.h"
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namespace {
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const uint32_t kExtractCompositeIdInIdx = 0;
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const uint32_t kInsertCompositeIdInIdx = 1;
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} // namespace
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namespace spvtools {
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namespace opt {
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Pass::Status VectorDCE::Process(ir::IRContext* ctx) {
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InitializeProcessing(ctx);
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bool modified = false;
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for (ir::Function& function : *get_module()) {
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modified |= VectorDCEFunction(&function);
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}
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return (modified ? Status::SuccessWithChange : Status::SuccessWithoutChange);
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}
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bool VectorDCE::VectorDCEFunction(ir::Function* function) {
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LiveComponentMap live_components;
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FindLiveComponents(function, &live_components);
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return RewriteInstructions(function, live_components);
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}
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void VectorDCE::FindLiveComponents(ir::Function* function,
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LiveComponentMap* live_components) {
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std::vector<WorkListItem> work_list;
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// Prime the work list. We will assume that any instruction that does
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// not result in a vector is live.
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//
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// TODO: If we want to remove all of the dead code with the current
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// implementation, we will have to iterate VectorDCE and ADCE. That can be
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// avoided if we treat scalar results as if they are vectors with 1 element.
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//
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// Extending to structures and matrices is not as straight forward because of
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// the nesting. We cannot simply us a bit vector to keep track of which
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// components are live because of arbitrary nesting of structs.
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function->ForEachInst(
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[&work_list, this, live_components](ir::Instruction* current_inst) {
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bool is_vector = HasVectorResult(current_inst);
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if (!is_vector) {
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switch (current_inst->opcode()) {
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case SpvOpCompositeExtract:
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MarkExtractUseAsLive(current_inst, live_components, &work_list);
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break;
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default:
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MarkUsesAsLive(current_inst, all_components_live_,
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live_components, &work_list);
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break;
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}
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}
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});
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// Process the work list propagating liveness.
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for (uint32_t i = 0; i < work_list.size(); i++) {
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WorkListItem current_item = work_list[i];
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ir::Instruction* current_inst = current_item.instruction;
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switch (current_inst->opcode()) {
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case SpvOpCompositeInsert:
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MarkInsertUsesAsLive(current_item, live_components, &work_list);
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break;
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case SpvOpVectorShuffle:
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MarkVectorShuffleUsesAsLive(current_item, live_components, &work_list);
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break;
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case SpvOpCompositeConstruct:
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// TODO: If we have a vector parameter, then we can determine which
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// of its components are live.
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MarkUsesAsLive(current_inst, all_components_live_, live_components,
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&work_list);
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break;
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default:
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if (spvOpcodeIsScalarizable(current_inst->opcode())) {
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MarkUsesAsLive(current_inst, current_item.components, live_components,
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&work_list);
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} else {
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MarkUsesAsLive(current_inst, all_components_live_, live_components,
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&work_list);
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}
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break;
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}
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}
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}
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void VectorDCE::MarkExtractUseAsLive(const ir::Instruction* current_inst,
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LiveComponentMap* live_components,
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std::vector<WorkListItem>* work_list) {
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analysis::DefUseManager* def_use_mgr = context()->get_def_use_mgr();
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uint32_t operand_id =
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current_inst->GetSingleWordInOperand(kExtractCompositeIdInIdx);
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ir::Instruction* operand_inst = def_use_mgr->GetDef(operand_id);
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if (HasVectorResult(operand_inst)) {
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WorkListItem new_item;
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new_item.instruction = operand_inst;
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new_item.components.Set(current_inst->GetSingleWordInOperand(1));
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AddItemToWorkListIfNeeded(new_item, live_components, work_list);
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}
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}
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void VectorDCE::MarkInsertUsesAsLive(
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const VectorDCE::WorkListItem& current_item,
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LiveComponentMap* live_components,
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std::vector<VectorDCE::WorkListItem>* work_list) {
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analysis::DefUseManager* def_use_mgr = context()->get_def_use_mgr();
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uint32_t operand_id =
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current_item.instruction->GetSingleWordInOperand(kInsertCompositeIdInIdx);
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ir::Instruction* operand_inst = def_use_mgr->GetDef(operand_id);
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WorkListItem new_item;
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new_item.instruction = operand_inst;
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new_item.components = current_item.components;
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new_item.components.Clear(
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current_item.instruction->GetSingleWordInOperand(2));
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AddItemToWorkListIfNeeded(new_item, live_components, work_list);
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}
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void VectorDCE::MarkVectorShuffleUsesAsLive(
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const WorkListItem& current_item,
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VectorDCE::LiveComponentMap* live_components,
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std::vector<WorkListItem>* work_list) {
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analysis::DefUseManager* def_use_mgr = context()->get_def_use_mgr();
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WorkListItem first_operand;
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first_operand.instruction =
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def_use_mgr->GetDef(current_item.instruction->GetSingleWordInOperand(0));
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WorkListItem second_operand;
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second_operand.instruction =
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def_use_mgr->GetDef(current_item.instruction->GetSingleWordInOperand(1));
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analysis::TypeManager* type_mgr = context()->get_type_mgr();
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analysis::Vector* first_type =
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type_mgr->GetType(first_operand.instruction->type_id())->AsVector();
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uint32_t size_of_first_operand = first_type->element_count();
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for (uint32_t in_op = 2; in_op < current_item.instruction->NumInOperands();
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++in_op) {
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uint32_t index = current_item.instruction->GetSingleWordInOperand(in_op);
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if (current_item.components.Get(in_op - 2)) {
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if (index < size_of_first_operand) {
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first_operand.components.Set(index);
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} else {
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second_operand.components.Set(index - size_of_first_operand);
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}
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}
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}
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AddItemToWorkListIfNeeded(first_operand, live_components, work_list);
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AddItemToWorkListIfNeeded(second_operand, live_components, work_list);
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}
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void VectorDCE::MarkUsesAsLive(
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ir::Instruction* current_inst, const utils::BitVector& live_elements,
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LiveComponentMap* live_components,
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std::vector<VectorDCE::WorkListItem>* work_list) {
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analysis::DefUseManager* def_use_mgr = context()->get_def_use_mgr();
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current_inst->ForEachInId([&work_list, &live_elements, this, live_components,
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def_use_mgr](uint32_t* operand_id) {
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ir::Instruction* operand_inst = def_use_mgr->GetDef(*operand_id);
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if (HasVectorResult(operand_inst)) {
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WorkListItem new_item;
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new_item.instruction = operand_inst;
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new_item.components = live_elements;
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AddItemToWorkListIfNeeded(new_item, live_components, work_list);
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}
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});
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}
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bool VectorDCE::HasVectorResult(const ir::Instruction* inst) const {
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analysis::TypeManager* type_mgr = context()->get_type_mgr();
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if (inst->type_id() == 0) {
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return false;
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}
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const analysis::Type* current_type = type_mgr->GetType(inst->type_id());
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bool is_vector = current_type->AsVector() != nullptr;
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return is_vector;
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}
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bool VectorDCE::RewriteInstructions(
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ir::Function* function,
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const VectorDCE::LiveComponentMap& live_components) {
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bool modified = false;
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function->ForEachInst(
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[&modified, this, live_components](ir::Instruction* current_inst) {
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if (!context()->IsCombinatorInstruction(current_inst)) {
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return;
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}
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auto live_component = live_components.find(current_inst->result_id());
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if (live_component == live_components.end()) {
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// If this instruction is not in live_components then it does not
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// produce a vector, or it is never referenced and ADCE will remove
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// it. No point in trying to differentiate.
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return;
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}
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// If no element in the current instruction is used replace it with an
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// OpUndef.
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if (live_component->second.Empty()) {
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modified = true;
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uint32_t undef_id = this->Type2Undef(current_inst->type_id());
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context()->KillNamesAndDecorates(current_inst);
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context()->ReplaceAllUsesWith(current_inst->result_id(), undef_id);
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context()->KillInst(current_inst);
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return;
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}
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switch (current_inst->opcode()) {
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case SpvOpCompositeInsert: {
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// If the value being inserted is not live, then we can skip the
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// insert.
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uint32_t insert_index = current_inst->GetSingleWordInOperand(2);
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if (!live_component->second.Get(insert_index)) {
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modified = true;
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context()->KillNamesAndDecorates(current_inst->result_id());
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uint32_t composite_id =
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current_inst->GetSingleWordInOperand(kInsertCompositeIdInIdx);
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context()->ReplaceAllUsesWith(current_inst->result_id(),
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composite_id);
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}
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} break;
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case SpvOpCompositeConstruct:
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// TODO: The members that are not live can be replaced by an undef
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// or constant. This will remove uses of those values, and possibly
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// create opportunities for ADCE.
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break;
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default:
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// Do nothing.
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break;
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}
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});
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return modified;
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}
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void VectorDCE::AddItemToWorkListIfNeeded(
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WorkListItem work_item, VectorDCE::LiveComponentMap* live_components,
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std::vector<WorkListItem>* work_list) {
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ir::Instruction* current_inst = work_item.instruction;
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auto it = live_components->find(current_inst->result_id());
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if (it == live_components->end()) {
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live_components->emplace(
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std::make_pair(current_inst->result_id(), work_item.components));
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work_list->emplace_back(work_item);
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} else {
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if (it->second.Or(work_item.components)) {
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work_list->emplace_back(work_item);
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}
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}
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}
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} // namespace opt
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} // namespace spvtools
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