mirror of
https://github.com/KhronosGroup/SPIRV-Tools
synced 2024-11-27 13:50:07 +00:00
309be423cc
This change implements instruction folding for arithmetic operations that are redundant, specifically: x + 0 = 0 + x = x x - 0 = x 0 - x = -x x * 0 = 0 * x = 0 x * 1 = 1 * x = x 0 / x = 0 x / 1 = x mix(a, b, 0) = a mix(a, b, 1) = b Cache ExtInst import id in feature manager This allows us to avoid string lookups during optimization; for now we just cache GLSL std450 import id but I can imagine caching more sets as they become utilized by the optimizer. Add tests for add/sub/mul/div/mix folding The tests cover scalar float/double cases, and some vector cases. Since most of the code for floating point folding is shared, the tests for vector folding are not as exhaustive as scalar. To test sub->negate folding I had to implement a custom fixture.
266 lines
10 KiB
C++
266 lines
10 KiB
C++
// Copyright (c) 2017 The Khronos Group Inc.
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// Copyright (c) 2017 Valve Corporation
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// Copyright (c) 2017 LunarG Inc.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "insert_extract_elim.h"
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#include "composite.h"
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#include "ir_context.h"
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#include "iterator.h"
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#include "latest_version_glsl_std_450_header.h"
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#include <vector>
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namespace spvtools {
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namespace opt {
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namespace {
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const uint32_t kConstantValueInIdx = 0;
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const uint32_t kExtractCompositeIdInIdx = 0;
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const uint32_t kInsertObjectIdInIdx = 0;
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const uint32_t kInsertCompositeIdInIdx = 1;
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const uint32_t kVectorShuffleVec1IdInIdx = 0;
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const uint32_t kVectorShuffleVec2IdInIdx = 1;
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const uint32_t kVectorShuffleCompsInIdx = 2;
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const uint32_t kTypeVectorCompTypeIdInIdx = 0;
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const uint32_t kTypeVectorLengthInIdx = 1;
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const uint32_t kTypeFloatWidthInIdx = 0;
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const uint32_t kExtInstSetIdInIdx = 0;
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const uint32_t kExtInstInstructionInIdx = 1;
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const uint32_t kFMixXIdInIdx = 2;
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const uint32_t kFMixYIdInIdx = 3;
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const uint32_t kFMixAIdInIdx = 4;
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} // anonymous namespace
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uint32_t InsertExtractElimPass::DoExtract(ir::Instruction* compInst,
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std::vector<uint32_t>* pExtIndices,
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uint32_t extOffset) {
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ir::Instruction* cinst = compInst;
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uint32_t cid = 0;
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uint32_t replId = 0;
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while (true) {
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if (cinst->opcode() == SpvOpCompositeInsert) {
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if (ExtInsMatch(*pExtIndices, cinst, extOffset)) {
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// Match! Use inserted value as replacement
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replId = cinst->GetSingleWordInOperand(kInsertObjectIdInIdx);
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break;
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} else if (ExtInsConflict(*pExtIndices, cinst, extOffset)) {
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// If extract has fewer indices than the insert, stop searching.
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// Otherwise increment offset of extract indices considered and
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// continue searching through the inserted value
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if (pExtIndices->size() - extOffset < cinst->NumInOperands() - 2) {
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break;
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} else {
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extOffset += cinst->NumInOperands() - 2;
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cid = cinst->GetSingleWordInOperand(kInsertObjectIdInIdx);
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}
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} else {
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// Consider next composite in insert chain
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cid = cinst->GetSingleWordInOperand(kInsertCompositeIdInIdx);
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}
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} else if (cinst->opcode() == SpvOpVectorShuffle) {
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// Get length of vector1
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uint32_t v1_id = cinst->GetSingleWordInOperand(kVectorShuffleVec1IdInIdx);
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ir::Instruction* v1_inst = get_def_use_mgr()->GetDef(v1_id);
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uint32_t v1_type_id = v1_inst->type_id();
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ir::Instruction* v1_type_inst = get_def_use_mgr()->GetDef(v1_type_id);
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uint32_t v1_len =
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v1_type_inst->GetSingleWordInOperand(kTypeVectorLengthInIdx);
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// Get shuffle idx
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uint32_t comp_idx = (*pExtIndices)[extOffset];
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uint32_t shuffle_idx =
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cinst->GetSingleWordInOperand(kVectorShuffleCompsInIdx + comp_idx);
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// If undefined, give up
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// TODO(greg-lunarg): Return OpUndef
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if (shuffle_idx == 0xFFFFFFFF) break;
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if (shuffle_idx < v1_len) {
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cid = v1_id;
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(*pExtIndices)[extOffset] = shuffle_idx;
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} else {
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cid = cinst->GetSingleWordInOperand(kVectorShuffleVec2IdInIdx);
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(*pExtIndices)[extOffset] = shuffle_idx - v1_len;
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}
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} else if (cinst->opcode() == SpvOpExtInst &&
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cinst->GetSingleWordInOperand(kExtInstSetIdInIdx) ==
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get_feature_mgr()->GetExtInstImportId_GLSLstd450() &&
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cinst->GetSingleWordInOperand(kExtInstInstructionInIdx) ==
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GLSLstd450FMix) {
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// If mixing value component is 0 or 1 we just match with x or y.
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// Otherwise give up.
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uint32_t comp_idx = (*pExtIndices)[extOffset];
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std::vector<uint32_t> aIndices = {comp_idx};
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uint32_t a_id = cinst->GetSingleWordInOperand(kFMixAIdInIdx);
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ir::Instruction* a_inst = get_def_use_mgr()->GetDef(a_id);
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uint32_t a_comp_id = DoExtract(a_inst, &aIndices, 0);
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if (a_comp_id == 0) break;
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ir::Instruction* a_comp_inst = get_def_use_mgr()->GetDef(a_comp_id);
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if (a_comp_inst->opcode() != SpvOpConstant) break;
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// If a value is not 32-bit, give up
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uint32_t a_comp_type_id = a_comp_inst->type_id();
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ir::Instruction* a_comp_type = get_def_use_mgr()->GetDef(a_comp_type_id);
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if (a_comp_type->GetSingleWordInOperand(kTypeFloatWidthInIdx) != 32)
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break;
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uint32_t u = a_comp_inst->GetSingleWordInOperand(kConstantValueInIdx);
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float* fp = reinterpret_cast<float*>(&u);
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if (*fp == 0.0)
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cid = cinst->GetSingleWordInOperand(kFMixXIdInIdx);
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else if (*fp == 1.0)
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cid = cinst->GetSingleWordInOperand(kFMixYIdInIdx);
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else
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break;
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} else {
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break;
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}
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cinst = get_def_use_mgr()->GetDef(cid);
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}
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// If search ended with CompositeConstruct or ConstantComposite
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// and the extract has one index, return the appropriate component.
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// TODO(greg-lunarg): Handle multiple-indices, ConstantNull, special
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// vector composition, and additional CompositeInsert.
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if (replId == 0 &&
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(cinst->opcode() == SpvOpCompositeConstruct ||
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cinst->opcode() == SpvOpConstantComposite) &&
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(*pExtIndices).size() - extOffset == 1) {
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uint32_t compIdx = (*pExtIndices)[extOffset];
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// If a vector CompositeConstruct we make sure all preceding
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// components are of component type (not vector composition).
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uint32_t ctype_id = cinst->type_id();
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ir::Instruction* ctype_inst = get_def_use_mgr()->GetDef(ctype_id);
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if (ctype_inst->opcode() == SpvOpTypeVector &&
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cinst->opcode() == SpvOpConstantComposite) {
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uint32_t vec_comp_type_id =
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ctype_inst->GetSingleWordInOperand(kTypeVectorCompTypeIdInIdx);
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if (compIdx < cinst->NumInOperands()) {
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uint32_t i = 0;
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for (; i <= compIdx; i++) {
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uint32_t compId = cinst->GetSingleWordInOperand(i);
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ir::Instruction* componentInst = get_def_use_mgr()->GetDef(compId);
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if (componentInst->type_id() != vec_comp_type_id) break;
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}
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if (i > compIdx) replId = cinst->GetSingleWordInOperand(compIdx);
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}
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} else {
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replId = cinst->GetSingleWordInOperand(compIdx);
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}
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}
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return replId;
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}
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bool InsertExtractElimPass::EliminateInsertExtract(ir::Function* func) {
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bool modified = false;
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for (auto bi = func->begin(); bi != func->end(); ++bi) {
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ir::Instruction* inst = &*bi->begin();
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while (inst) {
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switch (inst->opcode()) {
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case SpvOpCompositeExtract: {
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uint32_t cid = inst->GetSingleWordInOperand(kExtractCompositeIdInIdx);
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ir::Instruction* cinst = get_def_use_mgr()->GetDef(cid);
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// Capture extract indices
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std::vector<uint32_t> extIndices;
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uint32_t icnt = 0;
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inst->ForEachInOperand([&icnt, &extIndices](const uint32_t* idp) {
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if (icnt > 0) extIndices.push_back(*idp);
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++icnt;
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});
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// Offset of extract indices being compared to insert indices.
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// Offset increases as indices are matched.
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uint32_t replId = DoExtract(cinst, &extIndices, 0);
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if (replId != 0) {
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const uint32_t extId = inst->result_id();
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(void)context()->ReplaceAllUsesWith(extId, replId);
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inst = context()->KillInst(inst);
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modified = true;
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} else {
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inst = inst->NextNode();
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}
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} break;
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default:
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inst = inst->NextNode();
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break;
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}
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}
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}
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return modified;
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}
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void InsertExtractElimPass::Initialize(ir::IRContext* c) {
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InitializeProcessing(c);
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// Initialize extension whitelist
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InitExtensions();
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};
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bool InsertExtractElimPass::AllExtensionsSupported() const {
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// If any extension not in whitelist, return false
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for (auto& ei : get_module()->extensions()) {
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const char* extName =
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reinterpret_cast<const char*>(&ei.GetInOperand(0).words[0]);
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if (extensions_whitelist_.find(extName) == extensions_whitelist_.end())
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return false;
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}
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return true;
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}
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Pass::Status InsertExtractElimPass::ProcessImpl() {
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// Do not process if any disallowed extensions are enabled
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if (!AllExtensionsSupported()) return Status::SuccessWithoutChange;
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// Process all entry point functions.
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ProcessFunction pfn = [this](ir::Function* fp) {
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return EliminateInsertExtract(fp);
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};
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bool modified = ProcessEntryPointCallTree(pfn, get_module());
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return modified ? Status::SuccessWithChange : Status::SuccessWithoutChange;
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}
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InsertExtractElimPass::InsertExtractElimPass() {}
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Pass::Status InsertExtractElimPass::Process(ir::IRContext* c) {
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Initialize(c);
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return ProcessImpl();
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}
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void InsertExtractElimPass::InitExtensions() {
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extensions_whitelist_.clear();
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extensions_whitelist_.insert({
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"SPV_AMD_shader_explicit_vertex_parameter",
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"SPV_AMD_shader_trinary_minmax",
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"SPV_AMD_gcn_shader",
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"SPV_KHR_shader_ballot",
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"SPV_AMD_shader_ballot",
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"SPV_AMD_gpu_shader_half_float",
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"SPV_KHR_shader_draw_parameters",
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"SPV_KHR_subgroup_vote",
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"SPV_KHR_16bit_storage",
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"SPV_KHR_device_group",
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"SPV_KHR_multiview",
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"SPV_NVX_multiview_per_view_attributes",
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"SPV_NV_viewport_array2",
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"SPV_NV_stereo_view_rendering",
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"SPV_NV_sample_mask_override_coverage",
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"SPV_NV_geometry_shader_passthrough",
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"SPV_AMD_texture_gather_bias_lod",
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"SPV_KHR_storage_buffer_storage_class",
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"SPV_KHR_variable_pointers",
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"SPV_AMD_gpu_shader_int16",
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"SPV_KHR_post_depth_coverage",
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"SPV_KHR_shader_atomic_counter_ops",
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});
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}
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} // namespace opt
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} // namespace spvtools
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