mirror of
https://github.com/KhronosGroup/SPIRV-Tools
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fec56146a7
This PR implements the OpNot instruction for the add bit instruction synonym transformation. In addition, some code improvements have been made.
86 lines
3.2 KiB
C++
86 lines
3.2 KiB
C++
// Copyright (c) 2020 André Perez Maselco
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "source/fuzz/fuzzer_pass_add_bit_instruction_synonyms.h"
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#include "source/fuzz/fuzzer_util.h"
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#include "source/fuzz/instruction_descriptor.h"
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#include "source/fuzz/transformation_add_bit_instruction_synonym.h"
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namespace spvtools {
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namespace fuzz {
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FuzzerPassAddBitInstructionSynonyms::FuzzerPassAddBitInstructionSynonyms(
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opt::IRContext* ir_context, TransformationContext* transformation_context,
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FuzzerContext* fuzzer_context,
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protobufs::TransformationSequence* transformations)
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: FuzzerPass(ir_context, transformation_context, fuzzer_context,
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transformations) {}
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FuzzerPassAddBitInstructionSynonyms::~FuzzerPassAddBitInstructionSynonyms() =
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default;
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void FuzzerPassAddBitInstructionSynonyms::Apply() {
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for (auto& function : *GetIRContext()->module()) {
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for (auto& block : function) {
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for (auto& instruction : block) {
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// Randomly decides whether the transformation will be applied.
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if (!GetFuzzerContext()->ChoosePercentage(
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GetFuzzerContext()->GetChanceOfAddingBitInstructionSynonym())) {
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continue;
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}
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// TODO(https://github.com/KhronosGroup/SPIRV-Tools/issues/3557):
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// Right now we only support certain operations. When this issue is
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// addressed the following conditional can use the function
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// |spvOpcodeIsBit|.
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if (instruction.opcode() != SpvOpBitwiseOr &&
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instruction.opcode() != SpvOpBitwiseXor &&
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instruction.opcode() != SpvOpBitwiseAnd &&
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instruction.opcode() != SpvOpNot) {
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continue;
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}
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// Right now, only integer operands are supported.
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if (GetIRContext()
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->get_type_mgr()
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->GetType(instruction.type_id())
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->AsVector()) {
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continue;
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}
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// Make sure all bit indexes are defined as 32-bit unsigned integers.
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uint32_t width = GetIRContext()
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->get_type_mgr()
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->GetType(instruction.type_id())
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->AsInteger()
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->width();
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for (uint32_t i = 0; i < width; i++) {
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FindOrCreateIntegerConstant({i}, 32, false, false);
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}
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// Applies the add bit instruction synonym transformation.
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ApplyTransformation(TransformationAddBitInstructionSynonym(
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instruction.result_id(),
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GetFuzzerContext()->GetFreshIds(
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TransformationAddBitInstructionSynonym::GetRequiredFreshIdCount(
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GetIRContext(), &instruction))));
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}
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}
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}
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}
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} // namespace fuzz
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} // namespace spvtools
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