AuroraMiddleware/asio
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Use SSE2 intrinsics to allow the Cray compiler to work.

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This commit is contained in:
Christopher Kohlhoff 2014-06-28 21:44:40 +10:00
parent f1818afc93
commit 842f1c5df7
1 changed files with 8 additions and 0 deletions
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8
asio/include/asio/detail/gcc_x86_fenced_block.hpp
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@ -63,7 +63,11 @@ private:
static void lbarrier()
{
#if defined(__SSE2__)
# if (__GNUC__ >= 4)
__builtin_ia32_lfence();
# else // (__GNUC__ >= 4)
__asm__ __volatile__ ("lfence" ::: "memory");
# endif // (__GNUC__ >= 4)
#else // defined(__SSE2__)
barrier();
#endif // defined(__SSE2__)
@ -72,7 +76,11 @@ private:
static void sbarrier()
{
#if defined(__SSE2__)
# if (__GNUC__ >= 4)
__builtin_ia32_sfence();
# else // (__GNUC__ >= 4)
__asm__ __volatile__ ("sfence" ::: "memory");
# endif // (__GNUC__ >= 4)
#else // defined(__SSE2__)
barrier();
#endif // defined(__SSE2__)