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https://sourceware.org/git/glibc.git
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187 lines
5.5 KiB
ArmAsm
187 lines
5.5 KiB
ArmAsm
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/* Save current context.
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Copyright (C) 2004 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#include <sysdep.h>
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#include <ucontext-offsets.h>
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/* ??? Should be a better place for this that's asm friendly. */
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#define SIG_BLOCK 1
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ENTRY (__getcontext)
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#ifdef PROF
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ldgp gp, 0(pv)
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.set noat
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lda AT, _mcount
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jsr AT, (AT), _mcount
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.set at
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.prologue 1
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#else
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.prologue 0
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#endif
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bsr $0, __getcontext_x
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mov $31, $0
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ret
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END(__getcontext)
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weak_alias(__getcontext, getcontext)
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/* An internal routine used by getcontext and setcontext.
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The incomming return address register is $0. */
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.align 4
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.globl __getcontext_x
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.hidden __getcontext_x
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.usepv __getcontext_x, no
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cfi_startproc
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cfi_return_column (64)
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__getcontext_x:
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cfi_register (64, 0)
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/* Return value of getcontext. $0 is the only register
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whose value is not preserved. */
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stq $31, UC_SIGCTX+SC_REGS($16)
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/* Store all registers into the context. */
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stq $1, UC_SIGCTX+SC_REGS+1*8($16)
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stq $2, UC_SIGCTX+SC_REGS+2*8($16)
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stq $3, UC_SIGCTX+SC_REGS+3*8($16)
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stq $4, UC_SIGCTX+SC_REGS+4*8($16)
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stq $5, UC_SIGCTX+SC_REGS+5*8($16)
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stq $6, UC_SIGCTX+SC_REGS+6*8($16)
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stq $7, UC_SIGCTX+SC_REGS+7*8($16)
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stq $8, UC_SIGCTX+SC_REGS+8*8($16)
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stq $9, UC_SIGCTX+SC_REGS+9*8($16)
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stq $10, UC_SIGCTX+SC_REGS+10*8($16)
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stq $11, UC_SIGCTX+SC_REGS+11*8($16)
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stq $12, UC_SIGCTX+SC_REGS+12*8($16)
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stq $13, UC_SIGCTX+SC_REGS+13*8($16)
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stq $14, UC_SIGCTX+SC_REGS+14*8($16)
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stq $15, UC_SIGCTX+SC_REGS+15*8($16)
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stq $16, UC_SIGCTX+SC_REGS+16*8($16)
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stq $17, UC_SIGCTX+SC_REGS+17*8($16)
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stq $18, UC_SIGCTX+SC_REGS+18*8($16)
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stq $19, UC_SIGCTX+SC_REGS+19*8($16)
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stq $20, UC_SIGCTX+SC_REGS+20*8($16)
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stq $21, UC_SIGCTX+SC_REGS+21*8($16)
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stq $22, UC_SIGCTX+SC_REGS+22*8($16)
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stq $23, UC_SIGCTX+SC_REGS+23*8($16)
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stq $24, UC_SIGCTX+SC_REGS+24*8($16)
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stq $25, UC_SIGCTX+SC_REGS+25*8($16)
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stq $26, UC_SIGCTX+SC_REGS+26*8($16)
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stq $27, UC_SIGCTX+SC_REGS+27*8($16)
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stq $28, UC_SIGCTX+SC_REGS+28*8($16)
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stq $29, UC_SIGCTX+SC_REGS+29*8($16)
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stq $30, UC_SIGCTX+SC_REGS+30*8($16)
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stq $31, UC_SIGCTX+SC_REGS+31*8($16)
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stt $f0, UC_SIGCTX+SC_FPREGS+0*8($16)
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stt $f1, UC_SIGCTX+SC_FPREGS+1*8($16)
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stt $f2, UC_SIGCTX+SC_FPREGS+2*8($16)
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stt $f3, UC_SIGCTX+SC_FPREGS+3*8($16)
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stt $f4, UC_SIGCTX+SC_FPREGS+4*8($16)
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stt $f5, UC_SIGCTX+SC_FPREGS+5*8($16)
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stt $f6, UC_SIGCTX+SC_FPREGS+6*8($16)
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stt $f7, UC_SIGCTX+SC_FPREGS+7*8($16)
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stt $f8, UC_SIGCTX+SC_FPREGS+8*8($16)
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stt $f9, UC_SIGCTX+SC_FPREGS+9*8($16)
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stt $f10, UC_SIGCTX+SC_FPREGS+10*8($16)
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stt $f11, UC_SIGCTX+SC_FPREGS+11*8($16)
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stt $f12, UC_SIGCTX+SC_FPREGS+12*8($16)
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stt $f13, UC_SIGCTX+SC_FPREGS+13*8($16)
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stt $f14, UC_SIGCTX+SC_FPREGS+14*8($16)
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stt $f15, UC_SIGCTX+SC_FPREGS+15*8($16)
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stt $f16, UC_SIGCTX+SC_FPREGS+16*8($16)
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stt $f17, UC_SIGCTX+SC_FPREGS+17*8($16)
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stt $f18, UC_SIGCTX+SC_FPREGS+18*8($16)
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stt $f19, UC_SIGCTX+SC_FPREGS+19*8($16)
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stt $f20, UC_SIGCTX+SC_FPREGS+20*8($16)
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stt $f21, UC_SIGCTX+SC_FPREGS+21*8($16)
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stt $f22, UC_SIGCTX+SC_FPREGS+22*8($16)
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stt $f23, UC_SIGCTX+SC_FPREGS+23*8($16)
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stt $f24, UC_SIGCTX+SC_FPREGS+24*8($16)
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stt $f25, UC_SIGCTX+SC_FPREGS+25*8($16)
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stt $f26, UC_SIGCTX+SC_FPREGS+26*8($16)
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stt $f27, UC_SIGCTX+SC_FPREGS+27*8($16)
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stt $f28, UC_SIGCTX+SC_FPREGS+28*8($16)
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stt $f29, UC_SIGCTX+SC_FPREGS+29*8($16)
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stt $f30, UC_SIGCTX+SC_FPREGS+30*8($16)
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stt $f31, UC_SIGCTX+SC_FPREGS+31*8($16)
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mf_fpcr $f0
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lda $1, 8
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stt $f0, UC_SIGCTX+SC_FPCR($16)
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/* The return address of getcontext is the restart pc. */
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stq $26, UC_SIGCTX+SC_PC($16)
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/* Userlevel always has a processor status word of 8. */
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stq $1, UC_SIGCTX+SC_PS($16)
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/* Save registers around the syscall. We preserve $17
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for the benefit of swapcontext. */
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subq $30, 4*8, $30
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cfi_adjust_cfa_offset(4*8)
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stq $0, 0($30)
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cfi_rel_offset(64, 0)
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stq $16, 8($30)
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stq $17, 16($30)
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/* Save the current signal mask. Whee, there are three
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copies of this in the alpha ucontext_t. */
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lda $16, SIG_BLOCK
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lda $17, 0
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lda $0, __NR_osf_sigprocmask
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callsys
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ldq $16, 8($30)
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ldq $17, 16($30)
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stq $0, UC_OSF_SIGMASK($16)
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stq $0, UC_SIGCTX+SC_MASK($16)
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stq $0, UC_SIGMASK($16)
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stq $31, UC_SIGMASK + 1*8($16)
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stq $31, UC_SIGMASK + 2*8($16)
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stq $31, UC_SIGMASK + 3*8($16)
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stq $31, UC_SIGMASK + 4*8($16)
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stq $31, UC_SIGMASK + 5*8($16)
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stq $31, UC_SIGMASK + 6*8($16)
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stq $31, UC_SIGMASK + 7*8($16)
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stq $31, UC_SIGMASK + 8*8($16)
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stq $31, UC_SIGMASK + 9*8($16)
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stq $31, UC_SIGMASK +10*8($16)
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stq $31, UC_SIGMASK +11*8($16)
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stq $31, UC_SIGMASK +12*8($16)
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stq $31, UC_SIGMASK +13*8($16)
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stq $31, UC_SIGMASK +14*8($16)
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stq $31, UC_SIGMASK +15*8($16)
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ldq $0, 0($30)
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addq $30, 4*8, $30
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cfi_register (64, 0)
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cfi_adjust_cfa_offset(-4*8)
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ret $31, ($0), 1
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cfi_endproc
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.size __getcontext_x, .-__getcontext_x
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.type __getcontext_x, @function
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