2017-05-18 05:51:20 +00:00
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/* Optimized memcmp implementation for POWER7/PowerPC64.
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2020-01-01 00:14:33 +00:00
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Copyright (C) 2010-2020 Free Software Foundation, Inc.
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2017-05-18 05:51:20 +00:00
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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Prefer https to http for gnu.org and fsf.org URLs
Also, change sources.redhat.com to sourceware.org.
This patch was automatically generated by running the following shell
script, which uses GNU sed, and which avoids modifying files imported
from upstream:
sed -ri '
s,(http|ftp)(://(.*\.)?(gnu|fsf|sourceware)\.org($|[^.]|\.[^a-z])),https\2,g
s,(http|ftp)(://(.*\.)?)sources\.redhat\.com($|[^.]|\.[^a-z]),https\2sourceware.org\4,g
' \
$(find $(git ls-files) -prune -type f \
! -name '*.po' \
! -name 'ChangeLog*' \
! -path COPYING ! -path COPYING.LIB \
! -path manual/fdl-1.3.texi ! -path manual/lgpl-2.1.texi \
! -path manual/texinfo.tex ! -path scripts/config.guess \
! -path scripts/config.sub ! -path scripts/install-sh \
! -path scripts/mkinstalldirs ! -path scripts/move-if-change \
! -path INSTALL ! -path locale/programs/charmap-kw.h \
! -path po/libc.pot ! -path sysdeps/gnu/errlist.c \
! '(' -name configure \
-execdir test -f configure.ac -o -f configure.in ';' ')' \
! '(' -name preconfigure \
-execdir test -f preconfigure.ac ';' ')' \
-print)
and then by running 'make dist-prepare' to regenerate files built
from the altered files, and then executing the following to cleanup:
chmod a+x sysdeps/unix/sysv/linux/riscv/configure
# Omit irrelevant whitespace and comment-only changes,
# perhaps from a slightly-different Autoconf version.
git checkout -f \
sysdeps/csky/configure \
sysdeps/hppa/configure \
sysdeps/riscv/configure \
sysdeps/unix/sysv/linux/csky/configure
# Omit changes that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/powerpc/powerpc64/ppc-mcount.S: trailing lines
git checkout -f \
sysdeps/powerpc/powerpc64/ppc-mcount.S \
sysdeps/unix/sysv/linux/s390/s390-64/syscall.S
# Omit change that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S: last line does not end in newline
git checkout -f sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S
2019-09-07 05:40:42 +00:00
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<https://www.gnu.org/licenses/>. */
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2017-05-18 05:51:20 +00:00
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#include <sysdep.h>
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/* int [r3] memcmp (const char *s1 [r3],
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const char *s2 [r4],
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size_t size [r5]) */
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#ifndef MEMCMP
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# define MEMCMP memcmp
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#endif
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powerpc: Cleanup: use actual power8 assembly mnemonics
Some implementations in sysdeps/powerpc/powerpc64/power8/*.S still had
pre power8 compatible binutils hardcoded macros and were not using
.machine power8.
This patch should not have semantic changes, in fact it should have the
same exact code generated.
Tested that generated stripped shared objects are identical when
using "strip --remove-section=.note.gnu.build-id".
Checked on:
- powerpc64le, power9, build-many-glibcs.py, gcc 6.4.1 20180104, binutils 2.26.2.20160726
- powerpc64le, power8, debian 9, gcc 6.3.0 20170516, binutils 2.28
- powerpc64le, power9, ubuntu 19.04, gcc 8.3.0, binutils 2.32
- powerpc64le, power9, opensuse tumbleweed, gcc 9.1.1 20190527, binutils 2.32
- powerpc64, power9, debian 10, gcc 8.3.0, binutils 2.31.1
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Reviewed-by: Gabriel F. T. Gomes <gabrielftg@linux.ibm.com>
2019-06-27 18:44:17 +00:00
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.machine power8
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PowerPC64 ENTRY_TOCLESS
A number of functions in the sysdeps/powerpc/powerpc64/ tree don't use
or change r2, yet declare a global entry that sets up r2. This patch
fixes that problem, and consolidates the ENTRY and EALIGN macros.
* sysdeps/powerpc/powerpc64/sysdep.h: Formatting.
(NOPS, ENTRY_3): New macros.
(ENTRY): Rewrite.
(ENTRY_TOCLESS): Define.
(EALIGN, EALIGN_W_0, EALIGN_W_1, EALIGN_W_2, EALIGN_W_4, EALIGN_W_5,
EALIGN_W_6, EALIGN_W_7, EALIGN_W_8): Delete.
* sysdeps/powerpc/powerpc64/a2/memcpy.S: Replace EALIGN with ENTRY.
* sysdeps/powerpc/powerpc64/dl-trampoline.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_ceil.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_ceilf.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_floor.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_floorf.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_nearbyint.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_nearbyintf.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_rint.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_rintf.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_round.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_roundf.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_trunc.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_truncf.S: Likewise.
* sysdeps/powerpc/powerpc64/memset.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/fpu/s_finite.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/fpu/s_isinf.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/fpu/s_isnan.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strstr.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/e_expf.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_cosf.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_sinf.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strcasestr.S: Likewise.
* sysdeps/powerpc/powerpc64/addmul_1.S: Use ENTRY_TOCLESS.
* sysdeps/powerpc/powerpc64/cell/memcpy.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_copysign.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_copysignl.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_fabsl.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_isnan.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_llrint.S: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_llrintf.S: Likewise.
* sysdeps/powerpc/powerpc64/lshift.S: Likewise.
* sysdeps/powerpc/powerpc64/memcpy.S: Likewise.
* sysdeps/powerpc/powerpc64/mul_1.S: Likewise.
* sysdeps/powerpc/powerpc64/power4/memcmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power4/memcpy.S: Likewise.
* sysdeps/powerpc/powerpc64/power4/memset.S: Likewise.
* sysdeps/powerpc/powerpc64/power4/strncmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_ceil.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_ceilf.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_floor.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_floorf.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_llround.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_round.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_roundf.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_trunc.S: Likewise.
* sysdeps/powerpc/powerpc64/power5+/fpu/s_truncf.S: Likewise.
* sysdeps/powerpc/powerpc64/power5/fpu/s_isnan.S: Likewise.
* sysdeps/powerpc/powerpc64/power6/fpu/s_copysign.S: Likewise.
* sysdeps/powerpc/powerpc64/power6/fpu/s_isnan.S: Likewise.
* sysdeps/powerpc/powerpc64/power6/memcpy.S: Likewise.
* sysdeps/powerpc/powerpc64/power6/memset.S: Likewise.
* sysdeps/powerpc/powerpc64/power6x/fpu/s_isnan.S: Likewise.
* sysdeps/powerpc/powerpc64/power6x/fpu/s_llrint.S: Likewise.
* sysdeps/powerpc/powerpc64/power6x/fpu/s_llround.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/add_n.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/memchr.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/memcmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/memcpy.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/memmove.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/mempcpy.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/memrchr.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/memset.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/rawmemchr.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strcasecmp.S (strcasecmp_l):
Likewise.
* sysdeps/powerpc/powerpc64/power7/strchr.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strchrnul.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strcmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strlen.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strncmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strncpy.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strnlen.S: Likewise.
* sysdeps/powerpc/powerpc64/power7/strrchr.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_finite.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_isnan.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/fpu/s_llround.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/memcmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/memset.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strchr.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strcmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strcpy.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strlen.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strncmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strncpy.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strnlen.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strrchr.S: Likewise.
* sysdeps/powerpc/powerpc64/power8/strspn.S: Likewise.
* sysdeps/powerpc/powerpc64/power9/strcmp.S: Likewise.
* sysdeps/powerpc/powerpc64/power9/strncmp.S: Likewise.
* sysdeps/powerpc/powerpc64/strchr.S: Likewise.
* sysdeps/powerpc/powerpc64/strcmp.S: Likewise.
* sysdeps/powerpc/powerpc64/strlen.S: Likewise.
* sysdeps/powerpc/powerpc64/strncmp.S: Likewise.
* sysdeps/powerpc/powerpc64/ppc-mcount.S: Store LR earlier. Don't
add nop when SHARED.
* sysdeps/powerpc/powerpc64/start.S: Fix comment.
* sysdeps/powerpc/powerpc64/multiarch/strrchr-power8.S (ENTRY): Don't
define.
(ENTRY_TOCLESS): Define.
* sysdeps/powerpc/powerpc32/sysdep.h (ENTRY_TOCLESS): Define.
* sysdeps/powerpc/fpu/s_fma.S: Use ENTRY_TOCLESS.
* sysdeps/powerpc/fpu/s_fmaf.S: Likewise.
2017-06-14 01:15:50 +00:00
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ENTRY_TOCLESS (MEMCMP, 4)
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2017-05-18 05:51:20 +00:00
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CALL_MCOUNT 3
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#define rRTN r3
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#define rSTR1 r3 /* First string arg. */
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#define rSTR2 r4 /* Second string arg. */
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#define rN r5 /* Max string length. */
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#define rWORD1 r6 /* Current word in s1. */
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#define rWORD2 r7 /* Current word in s2. */
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#define rWORD3 r8 /* Next word in s1. */
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#define rWORD4 r9 /* Next word in s2. */
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#define rWORD5 r10 /* Next word in s1. */
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#define rWORD6 r11 /* Next word in s2. */
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#define rOFF8 r20 /* 8 bytes offset. */
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#define rOFF16 r21 /* 16 bytes offset. */
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#define rOFF24 r22 /* 24 bytes offset. */
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#define rOFF32 r23 /* 24 bytes offset. */
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#define rWORD6_SHIFT r24 /* Left rotation temp for rWORD8. */
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#define rWORD4_SHIFT r25 /* Left rotation temp for rWORD6. */
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#define rWORD2_SHIFT r26 /* Left rotation temp for rWORD4. */
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#define rWORD8_SHIFT r27 /* Left rotation temp for rWORD2. */
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#define rSHR r28 /* Unaligned shift right count. */
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#define rSHL r29 /* Unaligned shift left count. */
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#define rWORD7 r30 /* Next word in s1. */
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#define rWORD8 r31 /* Next word in s2. */
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#define rWORD8SAVE (-8)
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#define rWORD7SAVE (-16)
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#define rOFF8SAVE (-24)
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#define rOFF16SAVE (-32)
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#define rOFF24SAVE (-40)
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#define rOFF32SAVE (-48)
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#define rSHRSAVE (-56)
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#define rSHLSAVE (-64)
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#define rWORD8SHIFTSAVE (-72)
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#define rWORD2SHIFTSAVE (-80)
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#define rWORD4SHIFTSAVE (-88)
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#define rWORD6SHIFTSAVE (-96)
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#ifdef __LITTLE_ENDIAN__
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# define LD ldbrx
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#else
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# define LD ldx
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#endif
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xor r10, rSTR2, rSTR1
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cmpldi cr6, rN, 0
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cmpldi cr1, rN, 8
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clrldi. r0, r10, 61
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clrldi r12, rSTR1, 61
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cmpldi cr5, r12, 0
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beq- cr6, L(zeroLength)
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dcbt 0, rSTR1
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dcbt 0, rSTR2
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/* If less than 8 bytes or not aligned, use the unaligned
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byte loop. */
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blt cr1, L(bytealigned)
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bne L(unalignedqw)
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/* At this point we know both strings have the same alignment and the
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compare length is at least 8 bytes. r12 contains the low order
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3 bits of rSTR1 and cr5 contains the result of the logical compare
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of r12 to 0. If r12 == 0 then we are already double word
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aligned and can perform the DW aligned loop. */
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.align 4
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L(samealignment):
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or r11, rSTR2, rSTR1
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clrldi. r11, r11, 60
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beq L(qw_align)
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/* Try to align to QW else proceed to DW loop. */
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clrldi. r10, r10, 60
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bne L(DW)
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/* For the difference to reach QW alignment, load as DW. */
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clrrdi rSTR1, rSTR1, 3
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clrrdi rSTR2, rSTR2, 3
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subfic r10, r12, 8
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LD rWORD1, 0, rSTR1
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LD rWORD2, 0, rSTR2
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sldi r9, r10, 3
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subfic r9, r9, 64
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sld rWORD1, rWORD1, r9
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sld rWORD2, rWORD2, r9
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cmpld cr6, rWORD1, rWORD2
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addi rSTR1, rSTR1, 8
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addi rSTR2, rSTR2, 8
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bne cr6, L(ret_diff)
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subf rN, r10, rN
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cmpld cr6, r11, r12
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bgt cr6, L(qw_align)
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LD rWORD1, 0, rSTR1
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LD rWORD2, 0, rSTR2
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cmpld cr6, rWORD1, rWORD2
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addi rSTR1, rSTR1, 8
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addi rSTR2, rSTR2, 8
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bne cr6, L(different)
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cmpldi cr6, rN, 8
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ble cr6, L(zeroLength)
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addi rN, rN, -8
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/* Now both rSTR1 and rSTR2 are aligned to QW. */
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.align 4
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L(qw_align):
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vspltisb v0, 0
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srdi. r6, rN, 6
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li r8, 16
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li r10, 32
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li r11, 48
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ble cr0, L(lessthan64)
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mtctr r6
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vspltisb v8, 0
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vspltisb v6, 0
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/* Aligned vector loop. */
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.align 4
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L(aligned_loop):
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lvx v4, 0, rSTR1
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lvx v5, 0, rSTR2
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vcmpequb. v7, v6, v8
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bnl cr6, L(different3)
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lvx v6, rSTR1, r8
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lvx v8, rSTR2, r8
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vcmpequb. v7, v5, v4
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bnl cr6, L(different2)
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lvx v4, rSTR1, r10
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lvx v5, rSTR2, r10
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vcmpequb. v7, v6, v8
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bnl cr6, L(different3)
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lvx v6, rSTR1, r11
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lvx v8, rSTR2, r11
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vcmpequb. v7, v5, v4
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bnl cr6, L(different2)
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addi rSTR1, rSTR1, 64
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addi rSTR2, rSTR2, 64
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bdnz L(aligned_loop)
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vcmpequb. v7, v6, v8
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bnl cr6, L(different3)
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clrldi rN, rN, 58
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/* Handle remainder for aligned loop. */
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.align 4
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L(lessthan64):
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mr r9, rSTR1
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cmpdi cr6, rN, 0
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li rSTR1, 0
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blelr cr6
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lvx v4, 0, r9
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lvx v5, 0, rSTR2
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vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
addi rN, rN, -16
|
|
|
|
|
|
|
|
cmpdi cr6, rN, 0
|
|
|
|
blelr cr6
|
|
|
|
lvx v4, r9, r8
|
|
|
|
lvx v5, rSTR2, r8
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
addi rN, rN, -16
|
|
|
|
|
|
|
|
cmpdi cr6, rN, 0
|
|
|
|
blelr cr6
|
|
|
|
lvx v4, r9, r10
|
|
|
|
lvx v5, rSTR2, r10
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
addi rN, rN, -16
|
|
|
|
|
|
|
|
cmpdi cr6, rN, 0
|
|
|
|
blelr cr6
|
|
|
|
lvx v4, r9, r11
|
|
|
|
lvx v5, rSTR2, r11
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
blr
|
|
|
|
|
|
|
|
/* Calculate and return the difference. */
|
|
|
|
.align 4
|
|
|
|
L(different1):
|
|
|
|
cmpdi cr6, rN, 16
|
|
|
|
bge cr6, L(different2)
|
|
|
|
/* Discard unwanted bytes. */
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
lvsr v1, 0, rN
|
|
|
|
vperm v4, v4, v0, v1
|
|
|
|
vperm v5, v5, v0, v1
|
|
|
|
#else
|
|
|
|
lvsl v1, 0, rN
|
|
|
|
vperm v4, v0, v4, v1
|
|
|
|
vperm v5, v0, v5, v1
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v4, v5
|
|
|
|
li rRTN, 0
|
|
|
|
bltlr cr6
|
|
|
|
.align 4
|
|
|
|
L(different2):
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
/* Reverse bytes for direct comparison. */
|
|
|
|
lvsl v10, r0, r0
|
|
|
|
vspltisb v8, 15
|
|
|
|
vsububm v9, v8, v10
|
|
|
|
vperm v4, v4, v0, v9
|
|
|
|
vperm v5, v5, v0, v9
|
|
|
|
#endif
|
powerpc: Cleanup: use actual power8 assembly mnemonics
Some implementations in sysdeps/powerpc/powerpc64/power8/*.S still had
pre power8 compatible binutils hardcoded macros and were not using
.machine power8.
This patch should not have semantic changes, in fact it should have the
same exact code generated.
Tested that generated stripped shared objects are identical when
using "strip --remove-section=.note.gnu.build-id".
Checked on:
- powerpc64le, power9, build-many-glibcs.py, gcc 6.4.1 20180104, binutils 2.26.2.20160726
- powerpc64le, power8, debian 9, gcc 6.3.0 20170516, binutils 2.28
- powerpc64le, power9, ubuntu 19.04, gcc 8.3.0, binutils 2.32
- powerpc64le, power9, opensuse tumbleweed, gcc 9.1.1 20190527, binutils 2.32
- powerpc64, power9, debian 10, gcc 8.3.0, binutils 2.31.1
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Reviewed-by: Gabriel F. T. Gomes <gabrielftg@linux.ibm.com>
2019-06-27 18:44:17 +00:00
|
|
|
mfvrd r7, v4
|
|
|
|
mfvrd r9, v5
|
2017-05-18 05:51:20 +00:00
|
|
|
cmpld cr6, r7, r9
|
|
|
|
bne cr6, L(ret_diff)
|
|
|
|
/* Difference in second DW. */
|
|
|
|
vsldoi v4, v4, v4, 8
|
|
|
|
vsldoi v5, v5, v5, 8
|
powerpc: Cleanup: use actual power8 assembly mnemonics
Some implementations in sysdeps/powerpc/powerpc64/power8/*.S still had
pre power8 compatible binutils hardcoded macros and were not using
.machine power8.
This patch should not have semantic changes, in fact it should have the
same exact code generated.
Tested that generated stripped shared objects are identical when
using "strip --remove-section=.note.gnu.build-id".
Checked on:
- powerpc64le, power9, build-many-glibcs.py, gcc 6.4.1 20180104, binutils 2.26.2.20160726
- powerpc64le, power8, debian 9, gcc 6.3.0 20170516, binutils 2.28
- powerpc64le, power9, ubuntu 19.04, gcc 8.3.0, binutils 2.32
- powerpc64le, power9, opensuse tumbleweed, gcc 9.1.1 20190527, binutils 2.32
- powerpc64, power9, debian 10, gcc 8.3.0, binutils 2.31.1
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Reviewed-by: Gabriel F. T. Gomes <gabrielftg@linux.ibm.com>
2019-06-27 18:44:17 +00:00
|
|
|
mfvrd r7, v4
|
|
|
|
mfvrd r9, v5
|
2017-05-18 05:51:20 +00:00
|
|
|
cmpld cr6, r7, r9
|
|
|
|
L(ret_diff):
|
|
|
|
li rRTN, 1
|
|
|
|
bgtlr cr6
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
.align 4
|
|
|
|
L(different3):
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
/* Reverse bytes for direct comparison. */
|
|
|
|
vspltisb v9, 15
|
|
|
|
lvsl v10, r0, r0
|
|
|
|
vsububm v9, v9, v10
|
|
|
|
vperm v6, v6, v0, v9
|
|
|
|
vperm v8, v8, v0, v9
|
|
|
|
#endif
|
powerpc: Cleanup: use actual power8 assembly mnemonics
Some implementations in sysdeps/powerpc/powerpc64/power8/*.S still had
pre power8 compatible binutils hardcoded macros and were not using
.machine power8.
This patch should not have semantic changes, in fact it should have the
same exact code generated.
Tested that generated stripped shared objects are identical when
using "strip --remove-section=.note.gnu.build-id".
Checked on:
- powerpc64le, power9, build-many-glibcs.py, gcc 6.4.1 20180104, binutils 2.26.2.20160726
- powerpc64le, power8, debian 9, gcc 6.3.0 20170516, binutils 2.28
- powerpc64le, power9, ubuntu 19.04, gcc 8.3.0, binutils 2.32
- powerpc64le, power9, opensuse tumbleweed, gcc 9.1.1 20190527, binutils 2.32
- powerpc64, power9, debian 10, gcc 8.3.0, binutils 2.31.1
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Reviewed-by: Gabriel F. T. Gomes <gabrielftg@linux.ibm.com>
2019-06-27 18:44:17 +00:00
|
|
|
mfvrd r7, v6
|
|
|
|
mfvrd r9, v8
|
2017-05-18 05:51:20 +00:00
|
|
|
cmpld cr6, r7, r9
|
|
|
|
bne cr6, L(ret_diff)
|
|
|
|
/* Difference in second DW. */
|
|
|
|
vsldoi v6, v6, v6, 8
|
|
|
|
vsldoi v8, v8, v8, 8
|
powerpc: Cleanup: use actual power8 assembly mnemonics
Some implementations in sysdeps/powerpc/powerpc64/power8/*.S still had
pre power8 compatible binutils hardcoded macros and were not using
.machine power8.
This patch should not have semantic changes, in fact it should have the
same exact code generated.
Tested that generated stripped shared objects are identical when
using "strip --remove-section=.note.gnu.build-id".
Checked on:
- powerpc64le, power9, build-many-glibcs.py, gcc 6.4.1 20180104, binutils 2.26.2.20160726
- powerpc64le, power8, debian 9, gcc 6.3.0 20170516, binutils 2.28
- powerpc64le, power9, ubuntu 19.04, gcc 8.3.0, binutils 2.32
- powerpc64le, power9, opensuse tumbleweed, gcc 9.1.1 20190527, binutils 2.32
- powerpc64, power9, debian 10, gcc 8.3.0, binutils 2.31.1
Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Reviewed-by: Gabriel F. T. Gomes <gabrielftg@linux.ibm.com>
2019-06-27 18:44:17 +00:00
|
|
|
mfvrd r7, v6
|
|
|
|
mfvrd r9, v8
|
2017-05-18 05:51:20 +00:00
|
|
|
cmpld cr6, r7, r9
|
|
|
|
li rRTN, 1
|
|
|
|
bgtlr cr6
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
L(different):
|
|
|
|
cmpldi cr7, rN, 8
|
|
|
|
bgt cr7, L(end)
|
|
|
|
/* Skip unwanted bytes. */
|
|
|
|
sldi r8, rN, 3
|
|
|
|
subfic r8, r8, 64
|
|
|
|
srd rWORD1, rWORD1, r8
|
|
|
|
srd rWORD2, rWORD2, r8
|
|
|
|
cmpld cr6, rWORD1, rWORD2
|
|
|
|
li rRTN, 0
|
|
|
|
beqlr cr6
|
|
|
|
L(end):
|
|
|
|
li rRTN, 1
|
|
|
|
bgtlr cr6
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
L(unalignedqw):
|
|
|
|
/* Proceed to DW unaligned loop,if there is a chance of pagecross. */
|
|
|
|
rldicl r9, rSTR1, 0, 52
|
|
|
|
add r9, r9, rN
|
|
|
|
cmpldi cr0, r9, 4096-16
|
|
|
|
bgt cr0, L(unaligned)
|
|
|
|
rldicl r9, rSTR2, 0, 52
|
|
|
|
add r9, r9, rN
|
|
|
|
cmpldi cr0, r9, 4096-16
|
|
|
|
bgt cr0, L(unaligned)
|
|
|
|
li r0, 0
|
|
|
|
li r8, 16
|
|
|
|
vspltisb v0, 0
|
|
|
|
/* Check if rSTR1 is aligned to QW. */
|
|
|
|
andi. r11, rSTR1, 0xF
|
|
|
|
beq L(s1_align)
|
|
|
|
|
|
|
|
/* Compare 16B and align S1 to QW. */
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
lvsr v10, 0, rSTR1 /* Compute mask. */
|
|
|
|
lvsr v6, 0, rSTR2 /* Compute mask. */
|
|
|
|
#else
|
|
|
|
lvsl v10, 0, rSTR1 /* Compute mask. */
|
|
|
|
lvsl v6, 0, rSTR2 /* Compute mask. */
|
|
|
|
#endif
|
|
|
|
lvx v5, 0, rSTR2
|
|
|
|
lvx v9, rSTR2, r8
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v9, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v9, v6
|
|
|
|
#endif
|
|
|
|
lvx v4, 0, rSTR1
|
|
|
|
lvx v9, rSTR1, r8
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v4, v9, v4, v10
|
|
|
|
#else
|
|
|
|
vperm v4, v4, v9, v10
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
cmpldi cr6, rN, 16
|
|
|
|
ble cr6, L(zeroLength)
|
|
|
|
subfic r11, r11, 16
|
|
|
|
subf rN, r11, rN
|
|
|
|
add rSTR1, rSTR1, r11
|
|
|
|
add rSTR2, rSTR2, r11
|
|
|
|
|
|
|
|
/* As s1 is QW aligned prepare for unaligned loop. */
|
|
|
|
.align 4
|
|
|
|
L(s1_align):
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
lvsr v6, 0, rSTR2
|
|
|
|
#else
|
|
|
|
lvsl v6, 0, rSTR2
|
|
|
|
#endif
|
|
|
|
lvx v5, 0, rSTR2
|
|
|
|
srdi. r6, rN, 6
|
|
|
|
li r10, 32
|
|
|
|
li r11, 48
|
|
|
|
ble cr0, L(lessthan64_unalign)
|
|
|
|
mtctr r6
|
|
|
|
li r9, 64
|
|
|
|
/* Unaligned vector loop. */
|
|
|
|
.align 4
|
|
|
|
L(unalign_qwloop):
|
|
|
|
lvx v4, 0, rSTR1
|
|
|
|
lvx v10, rSTR2, r8
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v10, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v10, v6
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different2)
|
|
|
|
vor v5, v10, v10
|
|
|
|
lvx v4, rSTR1, r8
|
|
|
|
lvx v10, rSTR2, r10
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v10, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v10, v6
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different2)
|
|
|
|
vor v5, v10, v10
|
|
|
|
lvx v4, rSTR1, r10
|
|
|
|
lvx v10, rSTR2, r11
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v10, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v10, v6
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different2)
|
|
|
|
vor v5, v10, v10
|
|
|
|
lvx v4, rSTR1, r11
|
|
|
|
lvx v10, rSTR2, r9
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v10, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v10, v6
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different2)
|
|
|
|
vor v5, v10, v10
|
|
|
|
addi rSTR1, rSTR1, 64
|
|
|
|
addi rSTR2, rSTR2, 64
|
|
|
|
bdnz L(unalign_qwloop)
|
|
|
|
clrldi rN, rN, 58
|
|
|
|
/* Handle remainder for unaligned loop. */
|
|
|
|
.align 4
|
|
|
|
L(lessthan64_unalign):
|
|
|
|
mr r9, rSTR1
|
|
|
|
cmpdi cr6, rN, 0
|
|
|
|
li rSTR1, 0
|
|
|
|
blelr cr6
|
|
|
|
lvx v4, 0, r9
|
|
|
|
lvx v10, rSTR2, r8
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v10, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v10, v6
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
vor v5, v10, v10
|
|
|
|
addi rN, rN, -16
|
|
|
|
|
|
|
|
cmpdi cr6, rN, 0
|
|
|
|
blelr cr6
|
|
|
|
lvx v4, r9, r8
|
|
|
|
lvx v10, rSTR2, r10
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v10, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v10, v6
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
vor v5, v10, v10
|
|
|
|
addi rN, rN, -16
|
|
|
|
|
|
|
|
cmpdi cr6, rN, 0
|
|
|
|
blelr cr6
|
|
|
|
lvx v4, r9, r10
|
|
|
|
lvx v10, rSTR2, r11
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v10, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v10, v6
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
vor v5, v10, v10
|
|
|
|
addi rN, rN, -16
|
|
|
|
|
|
|
|
cmpdi cr6, rN, 0
|
|
|
|
blelr cr6
|
|
|
|
lvx v4, r9, r11
|
|
|
|
addi r11, r11, 16
|
|
|
|
lvx v10, rSTR2, r11
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
|
|
vperm v5, v10, v5, v6
|
|
|
|
#else
|
|
|
|
vperm v5, v5, v10, v6
|
|
|
|
#endif
|
|
|
|
vcmpequb. v7, v5, v4
|
|
|
|
bnl cr6, L(different1)
|
|
|
|
blr
|
|
|
|
|
|
|
|
/* Otherwise we know the two strings have the same alignment (but not
|
|
|
|
yet DW). So we force the string addresses to the next lower DW
|
|
|
|
boundary and special case this first DW using shift left to
|
|
|
|
eliminate bits preceding the first byte. Since we want to join the
|
|
|
|
normal (DW aligned) compare loop, starting at the second double word,
|
|
|
|
we need to adjust the length (rN) and special case the loop
|
|
|
|
versioning for the first DW. This ensures that the loop count is
|
|
|
|
correct and the first DW (shifted) is in the expected register pair. */
|
|
|
|
.align 4
|
|
|
|
L(DW):
|
|
|
|
std rWORD8, rWORD8SAVE(r1)
|
|
|
|
std rWORD7, rWORD7SAVE(r1)
|
|
|
|
std rOFF8, rOFF8SAVE(r1)
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std rOFF16, rOFF16SAVE(r1)
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std rOFF24, rOFF24SAVE(r1)
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std rOFF32, rOFF32SAVE(r1)
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cfi_offset(rWORD8, rWORD8SAVE)
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cfi_offset(rWORD7, rWORD7SAVE)
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cfi_offset(rOFF8, rOFF8SAVE)
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cfi_offset(rOFF16, rOFF16SAVE)
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cfi_offset(rOFF24, rOFF24SAVE)
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cfi_offset(rOFF32, rOFF32SAVE)
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li rOFF8,8
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li rOFF16,16
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li rOFF24,24
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li rOFF32,32
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clrrdi rSTR1, rSTR1, 3
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clrrdi rSTR2, rSTR2, 3
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beq cr5, L(DWaligned)
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add rN, rN, r12
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sldi rWORD6, r12, 3
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srdi r0, rN, 5 /* Divide by 32. */
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andi. r12, rN, 24 /* Get the DW remainder. */
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LD rWORD1, 0, rSTR1
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LD rWORD2, 0, rSTR2
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cmpldi cr1, r12, 16
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cmpldi cr7, rN, 32
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clrldi rN, rN, 61
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beq L(dPs4)
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mtctr r0
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bgt cr1, L(dPs3)
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beq cr1, L(dPs2)
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/* Remainder is 8. */
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.align 3
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L(dsP1):
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sld rWORD5, rWORD1, rWORD6
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sld rWORD6, rWORD2, rWORD6
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cmpld cr5, rWORD5, rWORD6
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blt cr7, L(dP1x)
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/* Do something useful in this cycle since we have to branch anyway. */
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LD rWORD1, rOFF8, rSTR1
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LD rWORD2, rOFF8, rSTR2
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cmpld cr7, rWORD1, rWORD2
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b L(dP1e)
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/* Remainder is 16. */
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.align 4
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L(dPs2):
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sld rWORD5, rWORD1, rWORD6
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sld rWORD6, rWORD2, rWORD6
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cmpld cr6, rWORD5, rWORD6
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blt cr7, L(dP2x)
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/* Do something useful in this cycle since we have to branch anyway. */
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LD rWORD7, rOFF8, rSTR1
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LD rWORD8, rOFF8, rSTR2
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cmpld cr5, rWORD7, rWORD8
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b L(dP2e)
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/* Remainder is 24. */
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.align 4
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L(dPs3):
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sld rWORD3, rWORD1, rWORD6
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sld rWORD4, rWORD2, rWORD6
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cmpld cr1, rWORD3, rWORD4
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b L(dP3e)
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/* Count is a multiple of 32, remainder is 0. */
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.align 4
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L(dPs4):
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mtctr r0
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sld rWORD1, rWORD1, rWORD6
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sld rWORD2, rWORD2, rWORD6
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cmpld cr7, rWORD1, rWORD2
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b L(dP4e)
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/* At this point we know both strings are double word aligned and the
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compare length is at least 8 bytes. */
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.align 4
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L(DWaligned):
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andi. r12, rN, 24 /* Get the DW remainder. */
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srdi r0, rN, 5 /* Divide by 32. */
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cmpldi cr1, r12, 16
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cmpldi cr7, rN, 32
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clrldi rN, rN, 61
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beq L(dP4)
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bgt cr1, L(dP3)
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beq cr1, L(dP2)
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/* Remainder is 8. */
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.align 4
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L(dP1):
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mtctr r0
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/* Normally we'd use rWORD7/rWORD8 here, but since we might exit early
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(8-15 byte compare), we want to use only volatile registers. This
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means we can avoid restoring non-volatile registers since we did not
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change any on the early exit path. The key here is the non-early
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exit path only cares about the condition code (cr5), not about which
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register pair was used. */
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LD rWORD5, 0, rSTR1
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LD rWORD6, 0, rSTR2
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cmpld cr5, rWORD5, rWORD6
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blt cr7, L(dP1x)
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LD rWORD1, rOFF8, rSTR1
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LD rWORD2, rOFF8, rSTR2
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cmpld cr7, rWORD1, rWORD2
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L(dP1e):
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LD rWORD3, rOFF16, rSTR1
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LD rWORD4, rOFF16, rSTR2
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cmpld cr1, rWORD3, rWORD4
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LD rWORD5, rOFF24, rSTR1
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LD rWORD6, rOFF24, rSTR2
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cmpld cr6, rWORD5, rWORD6
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bne cr5, L(dLcr5x)
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bne cr7, L(dLcr7x)
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LD rWORD7, rOFF32, rSTR1
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LD rWORD8, rOFF32, rSTR2
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addi rSTR1, rSTR1, 32
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addi rSTR2, rSTR2, 32
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bne cr1, L(dLcr1)
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cmpld cr5, rWORD7, rWORD8
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bdnz L(dLoop)
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bne cr6, L(dLcr6)
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ld rWORD8, rWORD8SAVE(r1)
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ld rWORD7, rWORD7SAVE(r1)
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.align 3
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L(dP1x):
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sldi. r12, rN, 3
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bne cr5, L(dLcr5x)
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subfic rN, r12, 64 /* Shift count is 64 - (rN * 8). */
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bne L(d00)
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ld rOFF8, rOFF8SAVE(r1)
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ld rOFF16, rOFF16SAVE(r1)
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ld rOFF24, rOFF24SAVE(r1)
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ld rOFF32, rOFF32SAVE(r1)
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li rRTN, 0
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blr
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/* Remainder is 16. */
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.align 4
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L(dP2):
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mtctr r0
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LD rWORD5, 0, rSTR1
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LD rWORD6, 0, rSTR2
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cmpld cr6, rWORD5, rWORD6
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blt cr7, L(dP2x)
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LD rWORD7, rOFF8, rSTR1
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LD rWORD8, rOFF8, rSTR2
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cmpld cr5, rWORD7, rWORD8
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L(dP2e):
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LD rWORD1, rOFF16, rSTR1
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LD rWORD2, rOFF16, rSTR2
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cmpld cr7, rWORD1, rWORD2
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LD rWORD3, rOFF24, rSTR1
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LD rWORD4, rOFF24, rSTR2
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cmpld cr1, rWORD3, rWORD4
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addi rSTR1, rSTR1, 8
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addi rSTR2, rSTR2, 8
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bne cr6, L(dLcr6)
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bne cr5, L(dLcr5)
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b L(dLoop2)
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.align 4
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L(dP2x):
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LD rWORD3, rOFF8, rSTR1
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LD rWORD4, rOFF8, rSTR2
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cmpld cr1, rWORD3, rWORD4
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sldi. r12, rN, 3
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bne cr6, L(dLcr6x)
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addi rSTR1, rSTR1, 8
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addi rSTR2, rSTR2, 8
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bne cr1, L(dLcr1x)
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subfic rN, r12, 64 /* Shift count is 64 - (rN * 8). */
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bne L(d00)
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ld rOFF8, rOFF8SAVE(r1)
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ld rOFF16, rOFF16SAVE(r1)
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ld rOFF24, rOFF24SAVE(r1)
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ld rOFF32, rOFF32SAVE(r1)
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li rRTN, 0
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blr
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/* Remainder is 24. */
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.align 4
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L(dP3):
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mtctr r0
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LD rWORD3, 0, rSTR1
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LD rWORD4, 0, rSTR2
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cmpld cr1, rWORD3, rWORD4
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L(dP3e):
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LD rWORD5, rOFF8, rSTR1
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LD rWORD6, rOFF8, rSTR2
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cmpld cr6, rWORD5, rWORD6
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blt cr7, L(dP3x)
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LD rWORD7, rOFF16, rSTR1
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LD rWORD8, rOFF16, rSTR2
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cmpld cr5, rWORD7, rWORD8
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LD rWORD1, rOFF24, rSTR1
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LD rWORD2, rOFF24, rSTR2
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cmpld cr7, rWORD1, rWORD2
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addi rSTR1, rSTR1, 16
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addi rSTR2, rSTR2, 16
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bne cr1, L(dLcr1)
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bne cr6, L(dLcr6)
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b L(dLoop1)
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/* Again we are on a early exit path (24-31 byte compare), we want to
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only use volatile registers and avoid restoring non-volatile
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registers. */
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.align 4
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L(dP3x):
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LD rWORD1, rOFF16, rSTR1
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LD rWORD2, rOFF16, rSTR2
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cmpld cr7, rWORD1, rWORD2
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sldi. r12, rN, 3
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bne cr1, L(dLcr1x)
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addi rSTR1, rSTR1, 16
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addi rSTR2, rSTR2, 16
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bne cr6, L(dLcr6x)
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subfic rN, r12, 64 /* Shift count is 64 - (rN * 8). */
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bne cr7, L(dLcr7x)
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bne L(d00)
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ld rOFF8, rOFF8SAVE(r1)
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ld rOFF16, rOFF16SAVE(r1)
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ld rOFF24, rOFF24SAVE(r1)
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ld rOFF32, rOFF32SAVE(r1)
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li rRTN, 0
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blr
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/* Count is a multiple of 32, remainder is 0. */
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.align 4
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L(dP4):
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mtctr r0
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LD rWORD1, 0, rSTR1
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LD rWORD2, 0, rSTR2
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cmpld cr7, rWORD1, rWORD2
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L(dP4e):
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LD rWORD3, rOFF8, rSTR1
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LD rWORD4, rOFF8, rSTR2
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cmpld cr1, rWORD3, rWORD4
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LD rWORD5, rOFF16, rSTR1
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LD rWORD6, rOFF16, rSTR2
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cmpld cr6, rWORD5, rWORD6
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LD rWORD7, rOFF24, rSTR1
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LD rWORD8, rOFF24, rSTR2
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addi rSTR1, rSTR1, 24
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addi rSTR2, rSTR2, 24
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cmpld cr5, rWORD7, rWORD8
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bne cr7, L(dLcr7)
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bne cr1, L(dLcr1)
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bdz- L(d24) /* Adjust CTR as we start with +4. */
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/* This is the primary loop. */
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.align 4
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L(dLoop):
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LD rWORD1, rOFF8, rSTR1
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LD rWORD2, rOFF8, rSTR2
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cmpld cr1, rWORD3, rWORD4
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bne cr6, L(dLcr6)
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L(dLoop1):
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LD rWORD3, rOFF16, rSTR1
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LD rWORD4, rOFF16, rSTR2
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cmpld cr6, rWORD5, rWORD6
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bne cr5, L(dLcr5)
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L(dLoop2):
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LD rWORD5, rOFF24, rSTR1
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LD rWORD6, rOFF24, rSTR2
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cmpld cr5, rWORD7, rWORD8
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bne cr7, L(dLcr7)
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L(dLoop3):
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LD rWORD7, rOFF32, rSTR1
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LD rWORD8, rOFF32, rSTR2
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addi rSTR1, rSTR1, 32
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addi rSTR2, rSTR2, 32
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bne cr1, L(dLcr1)
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cmpld cr7, rWORD1, rWORD2
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bdnz L(dLoop)
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L(dL4):
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cmpld cr1, rWORD3, rWORD4
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bne cr6, L(dLcr6)
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cmpld cr6, rWORD5, rWORD6
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bne cr5, L(dLcr5)
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cmpld cr5, rWORD7, rWORD8
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L(d44):
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bne cr7, L(dLcr7)
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L(d34):
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bne cr1, L(dLcr1)
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L(d24):
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bne cr6, L(dLcr6)
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L(d14):
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sldi. r12, rN, 3
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bne cr5, L(dLcr5)
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L(d04):
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ld rWORD8, rWORD8SAVE(r1)
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ld rWORD7, rWORD7SAVE(r1)
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subfic rN, r12, 64 /* Shift count is 64 - (rN * 8). */
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beq L(duzeroLength)
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/* At this point we have a remainder of 1 to 7 bytes to compare. Since
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we are aligned it is safe to load the whole double word, and use
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shift right double to eliminate bits beyond the compare length. */
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L(d00):
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LD rWORD1, rOFF8, rSTR1
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LD rWORD2, rOFF8, rSTR2
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srd rWORD1, rWORD1, rN
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srd rWORD2, rWORD2, rN
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cmpld cr7, rWORD1, rWORD2
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bne cr7, L(dLcr7x)
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ld rOFF8, rOFF8SAVE(r1)
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ld rOFF16, rOFF16SAVE(r1)
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ld rOFF24, rOFF24SAVE(r1)
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ld rOFF32, rOFF32SAVE(r1)
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li rRTN, 0
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blr
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.align 4
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L(dLcr7):
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ld rWORD8, rWORD8SAVE(r1)
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ld rWORD7, rWORD7SAVE(r1)
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L(dLcr7x):
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ld rOFF8, rOFF8SAVE(r1)
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ld rOFF16, rOFF16SAVE(r1)
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ld rOFF24, rOFF24SAVE(r1)
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ld rOFF32, rOFF32SAVE(r1)
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li rRTN, 1
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bgtlr cr7
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li rRTN, -1
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blr
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.align 4
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L(dLcr1):
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ld rWORD8, rWORD8SAVE(r1)
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ld rWORD7, rWORD7SAVE(r1)
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L(dLcr1x):
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ld rOFF8, rOFF8SAVE(r1)
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ld rOFF16, rOFF16SAVE(r1)
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ld rOFF24, rOFF24SAVE(r1)
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ld rOFF32, rOFF32SAVE(r1)
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li rRTN, 1
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bgtlr cr1
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li rRTN, -1
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blr
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.align 4
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L(dLcr6):
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ld rWORD8, rWORD8SAVE(r1)
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ld rWORD7, rWORD7SAVE(r1)
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L(dLcr6x):
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ld rOFF8, rOFF8SAVE(r1)
|
|
|
|
ld rOFF16, rOFF16SAVE(r1)
|
|
|
|
ld rOFF24, rOFF24SAVE(r1)
|
|
|
|
ld rOFF32, rOFF32SAVE(r1)
|
|
|
|
li rRTN, 1
|
|
|
|
bgtlr cr6
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
.align 4
|
|
|
|
L(dLcr5):
|
|
|
|
ld rWORD8, rWORD8SAVE(r1)
|
|
|
|
ld rWORD7, rWORD7SAVE(r1)
|
|
|
|
L(dLcr5x):
|
|
|
|
ld rOFF8, rOFF8SAVE(r1)
|
|
|
|
ld rOFF16, rOFF16SAVE(r1)
|
|
|
|
ld rOFF24, rOFF24SAVE(r1)
|
|
|
|
ld rOFF32, rOFF32SAVE(r1)
|
|
|
|
li rRTN, 1
|
|
|
|
bgtlr cr5
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
L(bytealigned):
|
|
|
|
mtctr rN
|
|
|
|
|
|
|
|
/* We need to prime this loop. This loop is swing modulo scheduled
|
|
|
|
to avoid pipe delays. The dependent instruction latencies (load to
|
|
|
|
compare to conditional branch) is 2 to 3 cycles. In this loop each
|
|
|
|
dispatch group ends in a branch and takes 1 cycle. Effectively
|
|
|
|
the first iteration of the loop only serves to load operands and
|
|
|
|
branches based on compares are delayed until the next loop.
|
|
|
|
|
|
|
|
So we must precondition some registers and condition codes so that
|
|
|
|
we don't exit the loop early on the first iteration. */
|
|
|
|
|
|
|
|
lbz rWORD1, 0(rSTR1)
|
|
|
|
lbz rWORD2, 0(rSTR2)
|
|
|
|
bdz L(b11)
|
|
|
|
cmpld cr7, rWORD1, rWORD2
|
|
|
|
lbz rWORD3, 1(rSTR1)
|
|
|
|
lbz rWORD4, 1(rSTR2)
|
|
|
|
bdz L(b12)
|
|
|
|
cmpld cr1, rWORD3, rWORD4
|
|
|
|
lbzu rWORD5, 2(rSTR1)
|
|
|
|
lbzu rWORD6, 2(rSTR2)
|
|
|
|
bdz L(b13)
|
|
|
|
.align 4
|
|
|
|
L(bLoop):
|
|
|
|
lbzu rWORD1, 1(rSTR1)
|
|
|
|
lbzu rWORD2, 1(rSTR2)
|
|
|
|
bne cr7, L(bLcr7)
|
|
|
|
|
|
|
|
cmpld cr6, rWORD5, rWORD6
|
|
|
|
bdz L(b3i)
|
|
|
|
|
|
|
|
lbzu rWORD3, 1(rSTR1)
|
|
|
|
lbzu rWORD4, 1(rSTR2)
|
|
|
|
bne cr1, L(bLcr1)
|
|
|
|
|
|
|
|
cmpld cr7, rWORD1, rWORD2
|
|
|
|
bdz L(b2i)
|
|
|
|
|
|
|
|
lbzu rWORD5, 1(rSTR1)
|
|
|
|
lbzu rWORD6, 1(rSTR2)
|
|
|
|
bne cr6, L(bLcr6)
|
|
|
|
|
|
|
|
cmpld cr1, rWORD3, rWORD4
|
|
|
|
bdnz L(bLoop)
|
|
|
|
|
|
|
|
/* We speculatively loading bytes before we have tested the previous
|
|
|
|
bytes. But we must avoid overrunning the length (in the ctr) to
|
|
|
|
prevent these speculative loads from causing a segfault. In this
|
|
|
|
case the loop will exit early (before the all pending bytes are
|
|
|
|
tested. In this case we must complete the pending operations
|
|
|
|
before returning. */
|
|
|
|
L(b1i):
|
|
|
|
bne cr7, L(bLcr7)
|
|
|
|
bne cr1, L(bLcr1)
|
|
|
|
b L(bx56)
|
|
|
|
.align 4
|
|
|
|
L(b2i):
|
|
|
|
bne cr6, L(bLcr6)
|
|
|
|
bne cr7, L(bLcr7)
|
|
|
|
b L(bx34)
|
|
|
|
.align 4
|
|
|
|
L(b3i):
|
|
|
|
bne cr1, L(bLcr1)
|
|
|
|
bne cr6, L(bLcr6)
|
|
|
|
b L(bx12)
|
|
|
|
.align 4
|
|
|
|
L(bLcr7):
|
|
|
|
li rRTN, 1
|
|
|
|
bgtlr cr7
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
L(bLcr1):
|
|
|
|
li rRTN, 1
|
|
|
|
bgtlr cr1
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
L(bLcr6):
|
|
|
|
li rRTN, 1
|
|
|
|
bgtlr cr6
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
|
|
|
|
L(b13):
|
|
|
|
bne cr7, L(bx12)
|
|
|
|
bne cr1, L(bx34)
|
|
|
|
L(bx56):
|
|
|
|
sub rRTN, rWORD5, rWORD6
|
|
|
|
blr
|
|
|
|
nop
|
|
|
|
L(b12):
|
|
|
|
bne cr7, L(bx12)
|
|
|
|
L(bx34):
|
|
|
|
sub rRTN, rWORD3, rWORD4
|
|
|
|
blr
|
|
|
|
L(b11):
|
|
|
|
L(bx12):
|
|
|
|
sub rRTN, rWORD1, rWORD2
|
|
|
|
blr
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
L(zeroLength):
|
|
|
|
li rRTN, 0
|
|
|
|
blr
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
/* At this point we know the strings have different alignment and the
|
|
|
|
compare length is at least 8 bytes. r12 contains the low order
|
|
|
|
3 bits of rSTR1 and cr5 contains the result of the logical compare
|
|
|
|
of r12 to 0. If r12 == 0 then rStr1 is double word
|
|
|
|
aligned and can perform the DWunaligned loop.
|
|
|
|
|
|
|
|
Otherwise we know that rSTR1 is not already DW aligned yet.
|
|
|
|
So we can force the string addresses to the next lower DW
|
|
|
|
boundary and special case this first DW using shift left to
|
|
|
|
eliminate bits preceding the first byte. Since we want to join the
|
|
|
|
normal (DWaligned) compare loop, starting at the second double word,
|
|
|
|
we need to adjust the length (rN) and special case the loop
|
|
|
|
versioning for the first DW. This ensures that the loop count is
|
|
|
|
correct and the first DW (shifted) is in the expected resister pair. */
|
|
|
|
L(unaligned):
|
|
|
|
std rWORD8, rWORD8SAVE(r1)
|
|
|
|
std rWORD7, rWORD7SAVE(r1)
|
|
|
|
std rOFF8, rOFF8SAVE(r1)
|
|
|
|
std rOFF16, rOFF16SAVE(r1)
|
|
|
|
std rOFF24, rOFF24SAVE(r1)
|
|
|
|
std rOFF32, rOFF32SAVE(r1)
|
|
|
|
cfi_offset(rWORD8, rWORD8SAVE)
|
|
|
|
cfi_offset(rWORD7, rWORD7SAVE)
|
|
|
|
cfi_offset(rOFF8, rOFF8SAVE)
|
|
|
|
cfi_offset(rOFF16, rOFF16SAVE)
|
|
|
|
cfi_offset(rOFF24, rOFF24SAVE)
|
|
|
|
cfi_offset(rOFF32, rOFF32SAVE)
|
|
|
|
li rOFF8,8
|
|
|
|
li rOFF16,16
|
|
|
|
li rOFF24,24
|
|
|
|
li rOFF32,32
|
|
|
|
std rSHL, rSHLSAVE(r1)
|
|
|
|
cfi_offset(rSHL, rSHLSAVE)
|
|
|
|
clrldi rSHL, rSTR2, 61
|
|
|
|
beq cr6, L(duzeroLength)
|
|
|
|
std rSHR, rSHRSAVE(r1)
|
|
|
|
cfi_offset(rSHR, rSHRSAVE)
|
|
|
|
beq cr5, L(DWunaligned)
|
|
|
|
std rWORD8_SHIFT, rWORD8SHIFTSAVE(r1)
|
|
|
|
cfi_offset(rWORD8_SHIFT, rWORD8SHIFTSAVE)
|
|
|
|
/* Adjust the logical start of rSTR2 to compensate for the extra bits
|
|
|
|
in the 1st rSTR1 DW. */
|
|
|
|
sub rWORD8_SHIFT, rSTR2, r12
|
|
|
|
/* But do not attempt to address the DW before that DW that contains
|
|
|
|
the actual start of rSTR2. */
|
|
|
|
clrrdi rSTR2, rSTR2, 3
|
|
|
|
std rWORD2_SHIFT, rWORD2SHIFTSAVE(r1)
|
|
|
|
/* Compute the left/right shift counts for the unaligned rSTR2,
|
|
|
|
compensating for the logical (DW aligned) start of rSTR1. */
|
|
|
|
clrldi rSHL, rWORD8_SHIFT, 61
|
|
|
|
clrrdi rSTR1, rSTR1, 3
|
|
|
|
std rWORD4_SHIFT, rWORD4SHIFTSAVE(r1)
|
|
|
|
sldi rSHL, rSHL, 3
|
|
|
|
cmpld cr5, rWORD8_SHIFT, rSTR2
|
|
|
|
add rN, rN, r12
|
|
|
|
sldi rWORD6, r12, 3
|
|
|
|
std rWORD6_SHIFT, rWORD6SHIFTSAVE(r1)
|
|
|
|
cfi_offset(rWORD2_SHIFT, rWORD2SHIFTSAVE)
|
|
|
|
cfi_offset(rWORD4_SHIFT, rWORD4SHIFTSAVE)
|
|
|
|
cfi_offset(rWORD6_SHIFT, rWORD6SHIFTSAVE)
|
|
|
|
subfic rSHR, rSHL, 64
|
|
|
|
srdi r0, rN, 5 /* Divide by 32. */
|
|
|
|
andi. r12, rN, 24 /* Get the DW remainder. */
|
|
|
|
/* We normally need to load 2 DWs to start the unaligned rSTR2, but in
|
|
|
|
this special case those bits may be discarded anyway. Also we
|
|
|
|
must avoid loading a DW where none of the bits are part of rSTR2 as
|
|
|
|
this may cross a page boundary and cause a page fault. */
|
|
|
|
li rWORD8, 0
|
|
|
|
blt cr5, L(dus0)
|
|
|
|
LD rWORD8, 0, rSTR2
|
|
|
|
addi rSTR2, rSTR2, 8
|
|
|
|
sld rWORD8, rWORD8, rSHL
|
|
|
|
|
|
|
|
L(dus0):
|
|
|
|
LD rWORD1, 0, rSTR1
|
|
|
|
LD rWORD2, 0, rSTR2
|
|
|
|
cmpldi cr1, r12, 16
|
|
|
|
cmpldi cr7, rN, 32
|
|
|
|
srd r12, rWORD2, rSHR
|
|
|
|
clrldi rN, rN, 61
|
|
|
|
beq L(duPs4)
|
|
|
|
mtctr r0
|
|
|
|
or rWORD8, r12, rWORD8
|
|
|
|
bgt cr1, L(duPs3)
|
|
|
|
beq cr1, L(duPs2)
|
|
|
|
|
|
|
|
/* Remainder is 8. */
|
|
|
|
.align 4
|
|
|
|
L(dusP1):
|
|
|
|
sld rWORD8_SHIFT, rWORD2, rSHL
|
|
|
|
sld rWORD7, rWORD1, rWORD6
|
|
|
|
sld rWORD8, rWORD8, rWORD6
|
|
|
|
bge cr7, L(duP1e)
|
|
|
|
/* At this point we exit early with the first double word compare
|
|
|
|
complete and remainder of 0 to 7 bytes. See L(du14) for details on
|
|
|
|
how we handle the remaining bytes. */
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
sldi. rN, rN, 3
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
cmpld cr7, rN, rSHR
|
|
|
|
beq L(duZeroReturn)
|
|
|
|
li r0, 0
|
|
|
|
ble cr7, L(dutrim)
|
|
|
|
LD rWORD2, rOFF8, rSTR2
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
b L(dutrim)
|
|
|
|
/* Remainder is 16. */
|
|
|
|
.align 4
|
|
|
|
L(duPs2):
|
|
|
|
sld rWORD6_SHIFT, rWORD2, rSHL
|
|
|
|
sld rWORD5, rWORD1, rWORD6
|
|
|
|
sld rWORD6, rWORD8, rWORD6
|
|
|
|
b L(duP2e)
|
|
|
|
/* Remainder is 24. */
|
|
|
|
.align 4
|
|
|
|
L(duPs3):
|
|
|
|
sld rWORD4_SHIFT, rWORD2, rSHL
|
|
|
|
sld rWORD3, rWORD1, rWORD6
|
|
|
|
sld rWORD4, rWORD8, rWORD6
|
|
|
|
b L(duP3e)
|
|
|
|
/* Count is a multiple of 32, remainder is 0. */
|
|
|
|
.align 4
|
|
|
|
L(duPs4):
|
|
|
|
mtctr r0
|
|
|
|
or rWORD8, r12, rWORD8
|
|
|
|
sld rWORD2_SHIFT, rWORD2, rSHL
|
|
|
|
sld rWORD1, rWORD1, rWORD6
|
|
|
|
sld rWORD2, rWORD8, rWORD6
|
|
|
|
b L(duP4e)
|
|
|
|
|
|
|
|
/* At this point we know rSTR1 is double word aligned and the
|
|
|
|
compare length is at least 8 bytes. */
|
|
|
|
.align 4
|
|
|
|
L(DWunaligned):
|
|
|
|
std rWORD8_SHIFT, rWORD8SHIFTSAVE(r1)
|
|
|
|
clrrdi rSTR2, rSTR2, 3
|
|
|
|
std rWORD2_SHIFT, rWORD2SHIFTSAVE(r1)
|
|
|
|
srdi r0, rN, 5 /* Divide by 32. */
|
|
|
|
std rWORD4_SHIFT, rWORD4SHIFTSAVE(r1)
|
|
|
|
andi. r12, rN, 24 /* Get the DW remainder. */
|
|
|
|
std rWORD6_SHIFT, rWORD6SHIFTSAVE(r1)
|
|
|
|
cfi_offset(rWORD8_SHIFT, rWORD8SHIFTSAVE)
|
|
|
|
cfi_offset(rWORD2_SHIFT, rWORD2SHIFTSAVE)
|
|
|
|
cfi_offset(rWORD4_SHIFT, rWORD4SHIFTSAVE)
|
|
|
|
cfi_offset(rWORD6_SHIFT, rWORD6SHIFTSAVE)
|
|
|
|
sldi rSHL, rSHL, 3
|
|
|
|
LD rWORD6, 0, rSTR2
|
|
|
|
LD rWORD8, rOFF8, rSTR2
|
|
|
|
addi rSTR2, rSTR2, 8
|
|
|
|
cmpldi cr1, r12, 16
|
|
|
|
cmpldi cr7, rN, 32
|
|
|
|
clrldi rN, rN, 61
|
|
|
|
subfic rSHR, rSHL, 64
|
|
|
|
sld rWORD6_SHIFT, rWORD6, rSHL
|
|
|
|
beq L(duP4)
|
|
|
|
mtctr r0
|
|
|
|
bgt cr1, L(duP3)
|
|
|
|
beq cr1, L(duP2)
|
|
|
|
|
|
|
|
/* Remainder is 8. */
|
|
|
|
.align 4
|
|
|
|
L(duP1):
|
|
|
|
srd r12, rWORD8, rSHR
|
|
|
|
LD rWORD7, 0, rSTR1
|
|
|
|
sld rWORD8_SHIFT, rWORD8, rSHL
|
|
|
|
or rWORD8, r12, rWORD6_SHIFT
|
|
|
|
blt cr7, L(duP1x)
|
|
|
|
L(duP1e):
|
|
|
|
LD rWORD1, rOFF8, rSTR1
|
|
|
|
LD rWORD2, rOFF8, rSTR2
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
sld rWORD2_SHIFT, rWORD2, rSHL
|
|
|
|
or rWORD2, r0, rWORD8_SHIFT
|
|
|
|
LD rWORD3, rOFF16, rSTR1
|
|
|
|
LD rWORD4, rOFF16, rSTR2
|
|
|
|
cmpld cr7, rWORD1, rWORD2
|
|
|
|
srd r12, rWORD4, rSHR
|
|
|
|
sld rWORD4_SHIFT, rWORD4, rSHL
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
or rWORD4, r12, rWORD2_SHIFT
|
|
|
|
LD rWORD5, rOFF24, rSTR1
|
|
|
|
LD rWORD6, rOFF24, rSTR2
|
|
|
|
cmpld cr1, rWORD3, rWORD4
|
|
|
|
srd r0, rWORD6, rSHR
|
|
|
|
sld rWORD6_SHIFT, rWORD6, rSHL
|
|
|
|
bne cr7, L(duLcr7)
|
|
|
|
or rWORD6, r0, rWORD4_SHIFT
|
|
|
|
cmpld cr6, rWORD5, rWORD6
|
|
|
|
b L(duLoop3)
|
|
|
|
.align 4
|
|
|
|
/* At this point we exit early with the first double word compare
|
|
|
|
complete and remainder of 0 to 7 bytes. See L(du14) for details on
|
|
|
|
how we handle the remaining bytes. */
|
|
|
|
L(duP1x):
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
sldi. rN, rN, 3
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
cmpld cr7, rN, rSHR
|
|
|
|
beq L(duZeroReturn)
|
|
|
|
li r0, 0
|
|
|
|
ble cr7, L(dutrim)
|
|
|
|
LD rWORD2, rOFF8, rSTR2
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
b L(dutrim)
|
|
|
|
/* Remainder is 16. */
|
|
|
|
.align 4
|
|
|
|
L(duP2):
|
|
|
|
srd r0, rWORD8, rSHR
|
|
|
|
LD rWORD5, 0, rSTR1
|
|
|
|
or rWORD6, r0, rWORD6_SHIFT
|
|
|
|
sld rWORD6_SHIFT, rWORD8, rSHL
|
|
|
|
L(duP2e):
|
|
|
|
LD rWORD7, rOFF8, rSTR1
|
|
|
|
LD rWORD8, rOFF8, rSTR2
|
|
|
|
cmpld cr6, rWORD5, rWORD6
|
|
|
|
srd r12, rWORD8, rSHR
|
|
|
|
sld rWORD8_SHIFT, rWORD8, rSHL
|
|
|
|
or rWORD8, r12, rWORD6_SHIFT
|
|
|
|
blt cr7, L(duP2x)
|
|
|
|
LD rWORD1, rOFF16, rSTR1
|
|
|
|
LD rWORD2, rOFF16, rSTR2
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
bne cr6, L(duLcr6)
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
sld rWORD2_SHIFT, rWORD2, rSHL
|
|
|
|
or rWORD2, r0, rWORD8_SHIFT
|
|
|
|
LD rWORD3, rOFF24, rSTR1
|
|
|
|
LD rWORD4, rOFF24, rSTR2
|
|
|
|
cmpld cr7, rWORD1, rWORD2
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
srd r12, rWORD4, rSHR
|
|
|
|
sld rWORD4_SHIFT, rWORD4, rSHL
|
|
|
|
or rWORD4, r12, rWORD2_SHIFT
|
|
|
|
addi rSTR1, rSTR1, 8
|
|
|
|
addi rSTR2, rSTR2, 8
|
|
|
|
cmpld cr1, rWORD3, rWORD4
|
|
|
|
b L(duLoop2)
|
|
|
|
.align 4
|
|
|
|
L(duP2x):
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
addi rSTR1, rSTR1, 8
|
|
|
|
addi rSTR2, rSTR2, 8
|
|
|
|
bne cr6, L(duLcr6)
|
|
|
|
sldi. rN, rN, 3
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
cmpld cr7, rN, rSHR
|
|
|
|
beq L(duZeroReturn)
|
|
|
|
li r0, 0
|
|
|
|
ble cr7, L(dutrim)
|
|
|
|
LD rWORD2, rOFF8, rSTR2
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
b L(dutrim)
|
|
|
|
|
|
|
|
/* Remainder is 24. */
|
|
|
|
.align 4
|
|
|
|
L(duP3):
|
|
|
|
srd r12, rWORD8, rSHR
|
|
|
|
LD rWORD3, 0, rSTR1
|
|
|
|
sld rWORD4_SHIFT, rWORD8, rSHL
|
|
|
|
or rWORD4, r12, rWORD6_SHIFT
|
|
|
|
L(duP3e):
|
|
|
|
LD rWORD5, rOFF8, rSTR1
|
|
|
|
LD rWORD6, rOFF8, rSTR2
|
|
|
|
cmpld cr1, rWORD3, rWORD4
|
|
|
|
srd r0, rWORD6, rSHR
|
|
|
|
sld rWORD6_SHIFT, rWORD6, rSHL
|
|
|
|
or rWORD6, r0, rWORD4_SHIFT
|
|
|
|
LD rWORD7, rOFF16, rSTR1
|
|
|
|
LD rWORD8, rOFF16, rSTR2
|
|
|
|
cmpld cr6, rWORD5, rWORD6
|
|
|
|
bne cr1, L(duLcr1)
|
|
|
|
srd r12, rWORD8, rSHR
|
|
|
|
sld rWORD8_SHIFT, rWORD8, rSHL
|
|
|
|
or rWORD8, r12, rWORD6_SHIFT
|
|
|
|
blt cr7, L(duP3x)
|
|
|
|
LD rWORD1, rOFF24, rSTR1
|
|
|
|
LD rWORD2, rOFF24, rSTR2
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
bne cr6, L(duLcr6)
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
sld rWORD2_SHIFT, rWORD2, rSHL
|
|
|
|
or rWORD2, r0, rWORD8_SHIFT
|
|
|
|
addi rSTR1, rSTR1, 16
|
|
|
|
addi rSTR2, rSTR2, 16
|
|
|
|
cmpld cr7, rWORD1, rWORD2
|
|
|
|
b L(duLoop1)
|
|
|
|
.align 4
|
|
|
|
L(duP3x):
|
|
|
|
addi rSTR1, rSTR1, 16
|
|
|
|
addi rSTR2, rSTR2, 16
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
bne cr6, L(duLcr6)
|
|
|
|
sldi. rN, rN, 3
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
cmpld cr7, rN, rSHR
|
|
|
|
beq L(duZeroReturn)
|
|
|
|
li r0, 0
|
|
|
|
ble cr7, L(dutrim)
|
|
|
|
LD rWORD2, rOFF8, rSTR2
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
b L(dutrim)
|
|
|
|
|
|
|
|
/* Count is a multiple of 32, remainder is 0. */
|
|
|
|
.align 4
|
|
|
|
L(duP4):
|
|
|
|
mtctr r0
|
|
|
|
srd r0, rWORD8, rSHR
|
|
|
|
LD rWORD1, 0, rSTR1
|
|
|
|
sld rWORD2_SHIFT, rWORD8, rSHL
|
|
|
|
or rWORD2, r0, rWORD6_SHIFT
|
|
|
|
L(duP4e):
|
|
|
|
LD rWORD3, rOFF8, rSTR1
|
|
|
|
LD rWORD4, rOFF8, rSTR2
|
|
|
|
cmpld cr7, rWORD1, rWORD2
|
|
|
|
srd r12, rWORD4, rSHR
|
|
|
|
sld rWORD4_SHIFT, rWORD4, rSHL
|
|
|
|
or rWORD4, r12, rWORD2_SHIFT
|
|
|
|
LD rWORD5, rOFF16, rSTR1
|
|
|
|
LD rWORD6, rOFF16, rSTR2
|
|
|
|
cmpld cr1, rWORD3, rWORD4
|
|
|
|
bne cr7, L(duLcr7)
|
|
|
|
srd r0, rWORD6, rSHR
|
|
|
|
sld rWORD6_SHIFT, rWORD6, rSHL
|
|
|
|
or rWORD6, r0, rWORD4_SHIFT
|
|
|
|
LD rWORD7, rOFF24, rSTR1
|
|
|
|
LD rWORD8, rOFF24, rSTR2
|
|
|
|
addi rSTR1, rSTR1, 24
|
|
|
|
addi rSTR2, rSTR2, 24
|
|
|
|
cmpld cr6, rWORD5, rWORD6
|
|
|
|
bne cr1, L(duLcr1)
|
|
|
|
srd r12, rWORD8, rSHR
|
|
|
|
sld rWORD8_SHIFT, rWORD8, rSHL
|
|
|
|
or rWORD8, r12, rWORD6_SHIFT
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
bdz L(du24) /* Adjust CTR as we start with +4. */
|
|
|
|
/* This is the primary loop. */
|
|
|
|
.align 4
|
|
|
|
L(duLoop):
|
|
|
|
LD rWORD1, rOFF8, rSTR1
|
|
|
|
LD rWORD2, rOFF8, rSTR2
|
|
|
|
cmpld cr1, rWORD3, rWORD4
|
|
|
|
bne cr6, L(duLcr6)
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
sld rWORD2_SHIFT, rWORD2, rSHL
|
|
|
|
or rWORD2, r0, rWORD8_SHIFT
|
|
|
|
L(duLoop1):
|
|
|
|
LD rWORD3, rOFF16, rSTR1
|
|
|
|
LD rWORD4, rOFF16, rSTR2
|
|
|
|
cmpld cr6, rWORD5, rWORD6
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
srd r12, rWORD4, rSHR
|
|
|
|
sld rWORD4_SHIFT, rWORD4, rSHL
|
|
|
|
or rWORD4, r12, rWORD2_SHIFT
|
|
|
|
L(duLoop2):
|
|
|
|
LD rWORD5, rOFF24, rSTR1
|
|
|
|
LD rWORD6, rOFF24, rSTR2
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
bne cr7, L(duLcr7)
|
|
|
|
srd r0, rWORD6, rSHR
|
|
|
|
sld rWORD6_SHIFT, rWORD6, rSHL
|
|
|
|
or rWORD6, r0, rWORD4_SHIFT
|
|
|
|
L(duLoop3):
|
|
|
|
LD rWORD7, rOFF32, rSTR1
|
|
|
|
LD rWORD8, rOFF32, rSTR2
|
|
|
|
addi rSTR1, rSTR1, 32
|
|
|
|
addi rSTR2, rSTR2, 32
|
|
|
|
cmpld cr7, rWORD1, rWORD2
|
|
|
|
bne cr1, L(duLcr1)
|
|
|
|
srd r12, rWORD8, rSHR
|
|
|
|
sld rWORD8_SHIFT, rWORD8, rSHL
|
|
|
|
or rWORD8, r12, rWORD6_SHIFT
|
|
|
|
bdnz L(duLoop)
|
|
|
|
|
|
|
|
L(duL4):
|
|
|
|
cmpld cr1, rWORD3, rWORD4
|
|
|
|
bne cr6, L(duLcr6)
|
|
|
|
cmpld cr6, rWORD5, rWORD6
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
cmpld cr5, rWORD7, rWORD8
|
|
|
|
L(du44):
|
|
|
|
bne cr7, L(duLcr7)
|
|
|
|
L(du34):
|
|
|
|
bne cr1, L(duLcr1)
|
|
|
|
L(du24):
|
|
|
|
bne cr6, L(duLcr6)
|
|
|
|
L(du14):
|
|
|
|
sldi. rN, rN, 3
|
|
|
|
bne cr5, L(duLcr5)
|
|
|
|
/* At this point we have a remainder of 1 to 7 bytes to compare. We use
|
|
|
|
shift right double to eliminate bits beyond the compare length.
|
|
|
|
|
|
|
|
However it may not be safe to load rWORD2 which may be beyond the
|
|
|
|
string length. So we compare the bit length of the remainder to
|
|
|
|
the right shift count (rSHR). If the bit count is less than or equal
|
|
|
|
we do not need to load rWORD2 (all significant bits are already in
|
|
|
|
rWORD8_SHIFT). */
|
|
|
|
cmpld cr7, rN, rSHR
|
|
|
|
beq L(duZeroReturn)
|
|
|
|
li r0, 0
|
|
|
|
ble cr7, L(dutrim)
|
|
|
|
LD rWORD2, rOFF8, rSTR2
|
|
|
|
srd r0, rWORD2, rSHR
|
|
|
|
.align 4
|
|
|
|
L(dutrim):
|
|
|
|
LD rWORD1, rOFF8, rSTR1
|
|
|
|
ld rWORD8, -8(r1)
|
|
|
|
subfic rN, rN, 64 /* Shift count is 64 - (rN * 8). */
|
|
|
|
or rWORD2, r0, rWORD8_SHIFT
|
|
|
|
ld rWORD7, rWORD7SAVE(r1)
|
|
|
|
ld rSHL, rSHLSAVE(r1)
|
|
|
|
srd rWORD1, rWORD1, rN
|
|
|
|
srd rWORD2, rWORD2, rN
|
|
|
|
ld rSHR, rSHRSAVE(r1)
|
|
|
|
ld rWORD8_SHIFT, rWORD8SHIFTSAVE(r1)
|
|
|
|
li rRTN, 0
|
|
|
|
cmpld cr7, rWORD1, rWORD2
|
|
|
|
ld rWORD2_SHIFT, rWORD2SHIFTSAVE(r1)
|
|
|
|
ld rWORD4_SHIFT, rWORD4SHIFTSAVE(r1)
|
|
|
|
beq cr7, L(dureturn24)
|
|
|
|
li rRTN, 1
|
|
|
|
ld rWORD6_SHIFT, rWORD6SHIFTSAVE(r1)
|
|
|
|
ld rOFF8, rOFF8SAVE(r1)
|
|
|
|
ld rOFF16, rOFF16SAVE(r1)
|
|
|
|
ld rOFF24, rOFF24SAVE(r1)
|
|
|
|
ld rOFF32, rOFF32SAVE(r1)
|
|
|
|
bgtlr cr7
|
|
|
|
li rRTN, -1
|
|
|
|
blr
|
|
|
|
.align 4
|
|
|
|
L(duLcr7):
|
|
|
|
ld rWORD8, rWORD8SAVE(r1)
|
|
|
|
ld rWORD7, rWORD7SAVE(r1)
|
|
|
|
li rRTN, 1
|
|
|
|
bgt cr7, L(dureturn29)
|
|
|
|
ld rSHL, rSHLSAVE(r1)
|
|
|
|
ld rSHR, rSHRSAVE(r1)
|
|
|
|
li rRTN, -1
|
|
|
|
b L(dureturn27)
|
|
|
|
.align 4
|
|
|
|
L(duLcr1):
|
|
|
|
ld rWORD8, rWORD8SAVE(r1)
|
|
|
|
ld rWORD7, rWORD7SAVE(r1)
|
|
|
|
li rRTN, 1
|
|
|
|
bgt cr1, L(dureturn29)
|
|
|
|
ld rSHL, rSHLSAVE(r1)
|
|
|
|
ld rSHR, rSHRSAVE(r1)
|
|
|
|
li rRTN, -1
|
|
|
|
b L(dureturn27)
|
|
|
|
.align 4
|
|
|
|
L(duLcr6):
|
|
|
|
ld rWORD8, rWORD8SAVE(r1)
|
|
|
|
ld rWORD7, rWORD7SAVE(r1)
|
|
|
|
li rRTN, 1
|
|
|
|
bgt cr6, L(dureturn29)
|
|
|
|
ld rSHL, rSHLSAVE(r1)
|
|
|
|
ld rSHR, rSHRSAVE(r1)
|
|
|
|
li rRTN, -1
|
|
|
|
b L(dureturn27)
|
|
|
|
.align 4
|
|
|
|
L(duLcr5):
|
|
|
|
ld rWORD8, rWORD8SAVE(r1)
|
|
|
|
ld rWORD7, rWORD7SAVE(r1)
|
|
|
|
li rRTN, 1
|
|
|
|
bgt cr5, L(dureturn29)
|
|
|
|
ld rSHL, rSHLSAVE(r1)
|
|
|
|
ld rSHR, rSHRSAVE(r1)
|
|
|
|
li rRTN, -1
|
|
|
|
b L(dureturn27)
|
|
|
|
|
|
|
|
.align 3
|
|
|
|
L(duZeroReturn):
|
|
|
|
li rRTN, 0
|
|
|
|
.align 4
|
|
|
|
L(dureturn):
|
|
|
|
ld rWORD8, rWORD8SAVE(r1)
|
|
|
|
ld rWORD7, rWORD7SAVE(r1)
|
|
|
|
L(dureturn29):
|
|
|
|
ld rSHL, rSHLSAVE(r1)
|
|
|
|
ld rSHR, rSHRSAVE(r1)
|
|
|
|
L(dureturn27):
|
|
|
|
ld rWORD8_SHIFT, rWORD8SHIFTSAVE(r1)
|
|
|
|
ld rWORD2_SHIFT, rWORD2SHIFTSAVE(r1)
|
|
|
|
ld rWORD4_SHIFT, rWORD4SHIFTSAVE(r1)
|
|
|
|
L(dureturn24):
|
|
|
|
ld rWORD6_SHIFT, rWORD6SHIFTSAVE(r1)
|
|
|
|
ld rOFF8, rOFF8SAVE(r1)
|
|
|
|
ld rOFF16, rOFF16SAVE(r1)
|
|
|
|
ld rOFF24, rOFF24SAVE(r1)
|
|
|
|
ld rOFF32, rOFF32SAVE(r1)
|
|
|
|
blr
|
|
|
|
|
|
|
|
L(duzeroLength):
|
|
|
|
ld rOFF8, rOFF8SAVE(r1)
|
|
|
|
ld rOFF16, rOFF16SAVE(r1)
|
|
|
|
ld rOFF24, rOFF24SAVE(r1)
|
|
|
|
ld rOFF32, rOFF32SAVE(r1)
|
|
|
|
li rRTN, 0
|
|
|
|
blr
|
|
|
|
|
|
|
|
END (MEMCMP)
|
|
|
|
libc_hidden_builtin_def (memcmp)
|
|
|
|
weak_alias (memcmp, bcmp)
|