2007-10-19 06:59:33 +00:00
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/* Copy SIZE bytes from SRC to DEST. For SUN4V Niagara-2.
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2019-01-01 00:11:28 +00:00
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Copyright (C) 2007-2019 Free Software Foundation, Inc.
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2007-10-19 06:59:33 +00:00
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This file is part of the GNU C Library.
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Contributed by David S. Miller (davem@davemloft.net)
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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2012-02-09 23:18:22 +00:00
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License along with the GNU C Library; if not, see
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Prefer https to http for gnu.org and fsf.org URLs
Also, change sources.redhat.com to sourceware.org.
This patch was automatically generated by running the following shell
script, which uses GNU sed, and which avoids modifying files imported
from upstream:
sed -ri '
s,(http|ftp)(://(.*\.)?(gnu|fsf|sourceware)\.org($|[^.]|\.[^a-z])),https\2,g
s,(http|ftp)(://(.*\.)?)sources\.redhat\.com($|[^.]|\.[^a-z]),https\2sourceware.org\4,g
' \
$(find $(git ls-files) -prune -type f \
! -name '*.po' \
! -name 'ChangeLog*' \
! -path COPYING ! -path COPYING.LIB \
! -path manual/fdl-1.3.texi ! -path manual/lgpl-2.1.texi \
! -path manual/texinfo.tex ! -path scripts/config.guess \
! -path scripts/config.sub ! -path scripts/install-sh \
! -path scripts/mkinstalldirs ! -path scripts/move-if-change \
! -path INSTALL ! -path locale/programs/charmap-kw.h \
! -path po/libc.pot ! -path sysdeps/gnu/errlist.c \
! '(' -name configure \
-execdir test -f configure.ac -o -f configure.in ';' ')' \
! '(' -name preconfigure \
-execdir test -f preconfigure.ac ';' ')' \
-print)
and then by running 'make dist-prepare' to regenerate files built
from the altered files, and then executing the following to cleanup:
chmod a+x sysdeps/unix/sysv/linux/riscv/configure
# Omit irrelevant whitespace and comment-only changes,
# perhaps from a slightly-different Autoconf version.
git checkout -f \
sysdeps/csky/configure \
sysdeps/hppa/configure \
sysdeps/riscv/configure \
sysdeps/unix/sysv/linux/csky/configure
# Omit changes that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/powerpc/powerpc64/ppc-mcount.S: trailing lines
git checkout -f \
sysdeps/powerpc/powerpc64/ppc-mcount.S \
sysdeps/unix/sysv/linux/s390/s390-64/syscall.S
# Omit change that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S: last line does not end in newline
git checkout -f sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S
2019-09-07 05:40:42 +00:00
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<https://www.gnu.org/licenses/>. */
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2007-10-19 06:59:33 +00:00
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#include <sysdep.h>
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#define ASI_BLK_INIT_QUAD_LDD_P 0xe2
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#define ASI_BLK_P 0xf0
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#define ASI_P 0x80
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#define ASI_PNF 0x82
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#define FPRS_FEF 0x04
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#define VISEntryHalf \
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rd %fprs, %o5; \
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wr %g0, FPRS_FEF, %fprs
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#define VISExitHalf \
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and %o5, FPRS_FEF, %o5; \
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wr %o5, 0x0, %fprs
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#define STORE_ASI ASI_BLK_INIT_QUAD_LDD_P
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#define LOAD(type,addr,dest) type [addr], dest
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#define LOAD_BLK(addr,dest) ldda [addr] ASI_BLK_P, dest
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#define STORE(type,src,addr) type src, [addr]
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#define STORE_BLK(src,addr) stda src, [addr] ASI_BLK_P
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#define STORE_INIT(src,addr) stxa src, [addr] STORE_ASI
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#ifndef XCC
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#define USE_BPR
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#define XCC xcc
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#endif
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#define FREG_FROB(x0, x1, x2, x3, x4, x5, x6, x7, x8) \
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faligndata %x0, %x1, %f0; \
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faligndata %x1, %x2, %f2; \
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faligndata %x2, %x3, %f4; \
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faligndata %x3, %x4, %f6; \
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faligndata %x4, %x5, %f8; \
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faligndata %x5, %x6, %f10; \
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faligndata %x6, %x7, %f12; \
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faligndata %x7, %x8, %f14;
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#define FREG_MOVE_1(x0) \
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2012-05-31 21:19:30 +00:00
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fsrc2 %x0, %f0;
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2007-10-19 06:59:33 +00:00
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#define FREG_MOVE_2(x0, x1) \
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2012-05-31 21:19:30 +00:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2;
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2007-10-19 06:59:33 +00:00
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#define FREG_MOVE_3(x0, x1, x2) \
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2012-05-31 21:19:30 +00:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4;
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2007-10-19 06:59:33 +00:00
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#define FREG_MOVE_4(x0, x1, x2, x3) \
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2012-05-31 21:19:30 +00:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6;
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2007-10-19 06:59:33 +00:00
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#define FREG_MOVE_5(x0, x1, x2, x3, x4) \
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2012-05-31 21:19:30 +00:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6; \
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fsrc2 %x4, %f8;
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2007-10-19 06:59:33 +00:00
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#define FREG_MOVE_6(x0, x1, x2, x3, x4, x5) \
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2012-05-31 21:19:30 +00:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6; \
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fsrc2 %x4, %f8; \
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fsrc2 %x5, %f10;
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2007-10-19 06:59:33 +00:00
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#define FREG_MOVE_7(x0, x1, x2, x3, x4, x5, x6) \
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2012-05-31 21:19:30 +00:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6; \
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fsrc2 %x4, %f8; \
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fsrc2 %x5, %f10; \
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fsrc2 %x6, %f12;
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2007-10-19 06:59:33 +00:00
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#define FREG_MOVE_8(x0, x1, x2, x3, x4, x5, x6, x7) \
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2012-05-31 21:19:30 +00:00
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fsrc2 %x0, %f0; \
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fsrc2 %x1, %f2; \
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fsrc2 %x2, %f4; \
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fsrc2 %x3, %f6; \
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fsrc2 %x4, %f8; \
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fsrc2 %x5, %f10; \
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fsrc2 %x6, %f12; \
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fsrc2 %x7, %f14;
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2007-10-19 06:59:33 +00:00
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#define FREG_LOAD_1(base, x0) \
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LOAD(ldd, base + 0x00, %x0)
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#define FREG_LOAD_2(base, x0, x1) \
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LOAD(ldd, base + 0x00, %x0); \
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LOAD(ldd, base + 0x08, %x1);
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#define FREG_LOAD_3(base, x0, x1, x2) \
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LOAD(ldd, base + 0x00, %x0); \
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LOAD(ldd, base + 0x08, %x1); \
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LOAD(ldd, base + 0x10, %x2);
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#define FREG_LOAD_4(base, x0, x1, x2, x3) \
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LOAD(ldd, base + 0x00, %x0); \
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LOAD(ldd, base + 0x08, %x1); \
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LOAD(ldd, base + 0x10, %x2); \
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LOAD(ldd, base + 0x18, %x3);
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#define FREG_LOAD_5(base, x0, x1, x2, x3, x4) \
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LOAD(ldd, base + 0x00, %x0); \
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LOAD(ldd, base + 0x08, %x1); \
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LOAD(ldd, base + 0x10, %x2); \
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LOAD(ldd, base + 0x18, %x3); \
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LOAD(ldd, base + 0x20, %x4);
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#define FREG_LOAD_6(base, x0, x1, x2, x3, x4, x5) \
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LOAD(ldd, base + 0x00, %x0); \
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LOAD(ldd, base + 0x08, %x1); \
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LOAD(ldd, base + 0x10, %x2); \
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LOAD(ldd, base + 0x18, %x3); \
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LOAD(ldd, base + 0x20, %x4); \
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LOAD(ldd, base + 0x28, %x5);
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#define FREG_LOAD_7(base, x0, x1, x2, x3, x4, x5, x6) \
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LOAD(ldd, base + 0x00, %x0); \
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LOAD(ldd, base + 0x08, %x1); \
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LOAD(ldd, base + 0x10, %x2); \
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LOAD(ldd, base + 0x18, %x3); \
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LOAD(ldd, base + 0x20, %x4); \
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LOAD(ldd, base + 0x28, %x5); \
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LOAD(ldd, base + 0x30, %x6);
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2014-11-24 09:33:45 +00:00
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#if IS_IN (libc)
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2010-02-26 07:52:07 +00:00
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2007-10-19 06:59:33 +00:00
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.register %g2,#scratch
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.register %g3,#scratch
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.register %g6,#scratch
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.text
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2012-03-29 05:35:26 +00:00
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ENTRY(__mempcpy_niagara2)
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ba,pt %XCC, 101f
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add %o0, %o2, %g5
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END(__mempcpy_niagara2)
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2007-10-19 06:59:33 +00:00
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.align 32
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2010-02-26 07:52:07 +00:00
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ENTRY(__memcpy_niagara2)
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2012-03-29 05:35:26 +00:00
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100: /* %o0=dst, %o1=src, %o2=len */
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mov %o0, %g5
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101:
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2010-02-26 07:52:07 +00:00
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# ifndef USE_BPR
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2008-10-11 08:52:58 +00:00
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srl %o2, 0, %o2
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2010-02-26 07:52:07 +00:00
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# endif
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2007-10-19 06:59:33 +00:00
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cmp %o2, 0
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be,pn %XCC, 85f
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218: or %o0, %o1, %o3
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cmp %o2, 16
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blu,a,pn %XCC, 80f
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or %o3, %o2, %o3
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/* 2 blocks (128 bytes) is the minimum we can do the block
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* copy with. We need to ensure that we'll iterate at least
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* once in the block copy loop. At worst we'll need to align
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* the destination to a 64-byte boundary which can chew up
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* to (64 - 1) bytes from the length before we perform the
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* block copy loop.
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*
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* However, the cut-off point, performance wise, is around
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* 4 64-byte blocks.
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*/
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cmp %o2, (4 * 64)
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blu,pt %XCC, 75f
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andcc %o3, 0x7, %g0
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/* %o0: dst
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* %o1: src
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* %o2: len (known to be >= 128)
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*
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* The block copy loops can use %o4, %g2, %g3 as
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* temporaries while copying the data. %o5 must
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* be preserved between VISEntryHalf and VISExitHalf
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*/
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LOAD(prefetch, %o1 + 0x000, #one_read)
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LOAD(prefetch, %o1 + 0x040, #one_read)
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LOAD(prefetch, %o1 + 0x080, #one_read)
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/* Align destination on 64-byte boundary. */
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andcc %o0, (64 - 1), %o4
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be,pt %XCC, 2f
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sub %o4, 64, %o4
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sub %g0, %o4, %o4 ! bytes to align dst
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sub %o2, %o4, %o2
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1: subcc %o4, 1, %o4
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LOAD(ldub, %o1, %g1)
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STORE(stb, %g1, %o0)
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add %o1, 1, %o1
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bne,pt %XCC, 1b
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add %o0, 1, %o0
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2:
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/* Clobbers o5/g1/g2/g3/g7/icc/xcc. We must preserve
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* o5 from here until we hit VISExitHalf.
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*/
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VISEntryHalf
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2014-05-17 18:20:27 +00:00
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membar #Sync
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2007-10-19 06:59:33 +00:00
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alignaddr %o1, %g0, %g0
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add %o1, (64 - 1), %o4
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andn %o4, (64 - 1), %o4
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andn %o2, (64 - 1), %g1
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sub %o2, %g1, %o2
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and %o1, (64 - 1), %g2
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add %o1, %g1, %o1
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sub %o0, %o4, %g3
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brz,pt %g2, 190f
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cmp %g2, 32
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blu,a 5f
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cmp %g2, 16
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cmp %g2, 48
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blu,a 4f
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cmp %g2, 40
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cmp %g2, 56
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blu 170f
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nop
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ba,a,pt %xcc, 180f
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4: /* 32 <= low bits < 48 */
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blu 150f
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nop
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ba,a,pt %xcc, 160f
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5: /* 0 < low bits < 32 */
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blu,a 6f
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cmp %g2, 8
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cmp %g2, 24
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blu 130f
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nop
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ba,a,pt %xcc, 140f
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6: /* 0 < low bits < 16 */
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bgeu 120f
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nop
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|
|
|
|
/* fall through for 0 < low bits < 8 */
|
|
|
|
|
110: sub %o4, 64, %g2
|
|
|
|
|
LOAD_BLK(%g2, %f0)
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
LOAD_BLK(%o4, %f16)
|
|
|
|
|
FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f14, f16)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
FREG_MOVE_8(f16, f18, f20, f22, f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
120: sub %o4, 56, %g2
|
|
|
|
|
FREG_LOAD_7(%g2, f0, f2, f4, f6, f8, f10, f12)
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
LOAD_BLK(%o4, %f16)
|
|
|
|
|
FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f16, f18)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
FREG_MOVE_7(f18, f20, f22, f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
130: sub %o4, 48, %g2
|
|
|
|
|
FREG_LOAD_6(%g2, f0, f2, f4, f6, f8, f10)
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
LOAD_BLK(%o4, %f16)
|
|
|
|
|
FREG_FROB(f0, f2, f4, f6, f8, f10, f16, f18, f20)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
FREG_MOVE_6(f20, f22, f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
140: sub %o4, 40, %g2
|
|
|
|
|
FREG_LOAD_5(%g2, f0, f2, f4, f6, f8)
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
LOAD_BLK(%o4, %f16)
|
|
|
|
|
FREG_FROB(f0, f2, f4, f6, f8, f16, f18, f20, f22)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
FREG_MOVE_5(f22, f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
150: sub %o4, 32, %g2
|
|
|
|
|
FREG_LOAD_4(%g2, f0, f2, f4, f6)
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
LOAD_BLK(%o4, %f16)
|
|
|
|
|
FREG_FROB(f0, f2, f4, f6, f16, f18, f20, f22, f24)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
FREG_MOVE_4(f24, f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
160: sub %o4, 24, %g2
|
|
|
|
|
FREG_LOAD_3(%g2, f0, f2, f4)
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
LOAD_BLK(%o4, %f16)
|
|
|
|
|
FREG_FROB(f0, f2, f4, f16, f18, f20, f22, f24, f26)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
FREG_MOVE_3(f26, f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
170: sub %o4, 16, %g2
|
|
|
|
|
FREG_LOAD_2(%g2, f0, f2)
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
LOAD_BLK(%o4, %f16)
|
|
|
|
|
FREG_FROB(f0, f2, f16, f18, f20, f22, f24, f26, f28)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
FREG_MOVE_2(f28, f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
180: sub %o4, 8, %g2
|
|
|
|
|
FREG_LOAD_1(%g2, f0)
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
LOAD_BLK(%o4, %f16)
|
|
|
|
|
FREG_FROB(f0, f16, f18, f20, f22, f24, f26, f28, f30)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
FREG_MOVE_1(f30)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
ba,pt %xcc, 195f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
190:
|
|
|
|
|
1: STORE_INIT(%g0, %o4 + %g3)
|
|
|
|
|
subcc %g1, 64, %g1
|
|
|
|
|
LOAD_BLK(%o4, %f0)
|
|
|
|
|
STORE_BLK(%f0, %o4 + %g3)
|
|
|
|
|
add %o4, 64, %o4
|
|
|
|
|
bne,pt %XCC, 1b
|
|
|
|
|
LOAD(prefetch, %o4 + 64, #one_read)
|
|
|
|
|
|
|
|
|
|
195:
|
|
|
|
|
add %o4, %g3, %o0
|
|
|
|
|
membar #Sync
|
|
|
|
|
|
|
|
|
|
VISExitHalf
|
|
|
|
|
|
|
|
|
|
/* %o2 contains any final bytes still needed to be copied
|
|
|
|
|
* over. If anything is left, we copy it one byte at a time.
|
|
|
|
|
*/
|
|
|
|
|
brz,pt %o2, 85f
|
|
|
|
|
sub %o0, %o1, %o3
|
|
|
|
|
ba,a,pt %XCC, 90f
|
|
|
|
|
|
|
|
|
|
.align 64
|
|
|
|
|
75: /* 16 < len <= 64 */
|
|
|
|
|
bne,pn %XCC, 75f
|
|
|
|
|
sub %o0, %o1, %o3
|
|
|
|
|
|
|
|
|
|
72:
|
|
|
|
|
andn %o2, 0xf, %o4
|
|
|
|
|
and %o2, 0xf, %o2
|
|
|
|
|
1: subcc %o4, 0x10, %o4
|
|
|
|
|
LOAD(ldx, %o1, %o5)
|
|
|
|
|
add %o1, 0x08, %o1
|
|
|
|
|
LOAD(ldx, %o1, %g1)
|
|
|
|
|
sub %o1, 0x08, %o1
|
|
|
|
|
STORE(stx, %o5, %o1 + %o3)
|
|
|
|
|
add %o1, 0x8, %o1
|
|
|
|
|
STORE(stx, %g1, %o1 + %o3)
|
|
|
|
|
bgu,pt %XCC, 1b
|
|
|
|
|
add %o1, 0x8, %o1
|
|
|
|
|
73: andcc %o2, 0x8, %g0
|
|
|
|
|
be,pt %XCC, 1f
|
|
|
|
|
nop
|
|
|
|
|
sub %o2, 0x8, %o2
|
|
|
|
|
LOAD(ldx, %o1, %o5)
|
|
|
|
|
STORE(stx, %o5, %o1 + %o3)
|
|
|
|
|
add %o1, 0x8, %o1
|
|
|
|
|
1: andcc %o2, 0x4, %g0
|
|
|
|
|
be,pt %XCC, 1f
|
|
|
|
|
nop
|
|
|
|
|
sub %o2, 0x4, %o2
|
|
|
|
|
LOAD(lduw, %o1, %o5)
|
|
|
|
|
STORE(stw, %o5, %o1 + %o3)
|
|
|
|
|
add %o1, 0x4, %o1
|
|
|
|
|
1: cmp %o2, 0
|
|
|
|
|
be,pt %XCC, 85f
|
|
|
|
|
nop
|
|
|
|
|
ba,pt %xcc, 90f
|
|
|
|
|
nop
|
|
|
|
|
|
|
|
|
|
75:
|
|
|
|
|
andcc %o0, 0x7, %g1
|
|
|
|
|
sub %g1, 0x8, %g1
|
|
|
|
|
be,pn %icc, 2f
|
|
|
|
|
sub %g0, %g1, %g1
|
|
|
|
|
sub %o2, %g1, %o2
|
|
|
|
|
|
|
|
|
|
1: subcc %g1, 1, %g1
|
|
|
|
|
LOAD(ldub, %o1, %o5)
|
|
|
|
|
STORE(stb, %o5, %o1 + %o3)
|
|
|
|
|
bgu,pt %icc, 1b
|
|
|
|
|
add %o1, 1, %o1
|
|
|
|
|
|
|
|
|
|
2: add %o1, %o3, %o0
|
|
|
|
|
andcc %o1, 0x7, %g1
|
|
|
|
|
bne,pt %icc, 8f
|
|
|
|
|
sll %g1, 3, %g1
|
|
|
|
|
|
|
|
|
|
cmp %o2, 16
|
|
|
|
|
bgeu,pt %icc, 72b
|
|
|
|
|
nop
|
|
|
|
|
ba,a,pt %xcc, 73b
|
|
|
|
|
|
|
|
|
|
8: mov 64, %o3
|
|
|
|
|
andn %o1, 0x7, %o1
|
|
|
|
|
LOAD(ldx, %o1, %g2)
|
|
|
|
|
sub %o3, %g1, %o3
|
|
|
|
|
andn %o2, 0x7, %o4
|
|
|
|
|
sllx %g2, %g1, %g2
|
|
|
|
|
1: add %o1, 0x8, %o1
|
|
|
|
|
LOAD(ldx, %o1, %g3)
|
|
|
|
|
subcc %o4, 0x8, %o4
|
|
|
|
|
srlx %g3, %o3, %o5
|
|
|
|
|
or %o5, %g2, %o5
|
|
|
|
|
STORE(stx, %o5, %o0)
|
|
|
|
|
add %o0, 0x8, %o0
|
|
|
|
|
bgu,pt %icc, 1b
|
|
|
|
|
sllx %g3, %g1, %g2
|
|
|
|
|
|
|
|
|
|
srl %g1, 3, %g1
|
|
|
|
|
andcc %o2, 0x7, %o2
|
|
|
|
|
be,pn %icc, 85f
|
|
|
|
|
add %o1, %g1, %o1
|
|
|
|
|
ba,pt %xcc, 90f
|
|
|
|
|
sub %o0, %o1, %o3
|
|
|
|
|
|
|
|
|
|
.align 64
|
|
|
|
|
80: /* 0 < len <= 16 */
|
|
|
|
|
andcc %o3, 0x3, %g0
|
|
|
|
|
bne,pn %XCC, 90f
|
|
|
|
|
sub %o0, %o1, %o3
|
|
|
|
|
|
|
|
|
|
1:
|
|
|
|
|
subcc %o2, 4, %o2
|
|
|
|
|
LOAD(lduw, %o1, %g1)
|
|
|
|
|
STORE(stw, %g1, %o1 + %o3)
|
|
|
|
|
bgu,pt %XCC, 1b
|
|
|
|
|
add %o1, 4, %o1
|
|
|
|
|
|
|
|
|
|
85: retl
|
|
|
|
|
mov %g5, %o0
|
|
|
|
|
|
|
|
|
|
.align 32
|
|
|
|
|
90:
|
|
|
|
|
subcc %o2, 1, %o2
|
|
|
|
|
LOAD(ldub, %o1, %g1)
|
|
|
|
|
STORE(stb, %g1, %o1 + %o3)
|
|
|
|
|
bgu,pt %XCC, 90b
|
|
|
|
|
add %o1, 1, %o1
|
|
|
|
|
retl
|
|
|
|
|
mov %g5, %o0
|
|
|
|
|
|
2010-02-26 07:52:07 +00:00
|
|
|
END(__memcpy_niagara2)
|
2007-10-19 06:59:33 +00:00
|
|
|
|
2010-02-26 07:52:07 +00:00
|
|
|
#endif
|
