2024-02-20 16:59:39 +00:00
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/* Helper for single-precision AdvSIMD routines which depend on exp
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Copyright (C) 2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef AARCH64_FPU_V_EXPF_INLINE_H
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#define AARCH64_FPU_V_EXPF_INLINE_H
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#include "v_math.h"
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struct v_expf_data
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{
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float32x4_t poly[5];
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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float32x4_t shift;
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float invln2_and_ln2[4];
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2024-02-20 16:59:39 +00:00
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};
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/* maxerr: 1.45358 +0.5 ulp. */
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#define V_EXPF_DATA \
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{ \
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.poly = { V4 (0x1.0e4020p-7f), V4 (0x1.573e2ep-5f), V4 (0x1.555e66p-3f), \
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V4 (0x1.fffdb6p-2f), V4 (0x1.ffffecp-1f) }, \
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.shift = V4 (0x1.8p23f), \
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.invln2_and_ln2 = { 0x1.715476p+0f, 0x1.62e4p-1f, 0x1.7f7d1cp-20f, 0 }, \
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}
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#define ExponentBias v_u32 (0x3f800000) /* asuint(1.0f). */
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#define C(i) d->poly[i]
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static inline float32x4_t
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v_expf_inline (float32x4_t x, const struct v_expf_data *d)
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{
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/* Helper routine for calculating exp(x).
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Copied from v_expf.c, with all special-case handling removed - the
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calling routine should handle special values if required. */
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/* exp(x) = 2^n (1 + poly(r)), with 1 + poly(r) in [1/sqrt(2),sqrt(2)]
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x = ln2*n + r, with r in [-ln2/2, ln2/2]. */
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float32x4_t n, r, z;
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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float32x4_t invln2_and_ln2 = vld1q_f32 (d->invln2_and_ln2);
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z = vfmaq_laneq_f32 (d->shift, x, invln2_and_ln2, 0);
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2024-02-20 16:59:39 +00:00
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n = vsubq_f32 (z, d->shift);
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aarch64: Fix AdvSIMD libmvec routines for big-endian
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-02 15:43:13 +00:00
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r = vfmsq_laneq_f32 (x, n, invln2_and_ln2, 1);
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r = vfmsq_laneq_f32 (r, n, invln2_and_ln2, 2);
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2024-02-20 16:59:39 +00:00
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uint32x4_t e = vshlq_n_u32 (vreinterpretq_u32_f32 (z), 23);
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float32x4_t scale = vreinterpretq_f32_u32 (vaddq_u32 (e, ExponentBias));
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/* Custom order-4 Estrin avoids building high order monomial. */
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float32x4_t r2 = vmulq_f32 (r, r);
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float32x4_t p, q, poly;
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p = vfmaq_f32 (C (1), C (0), r);
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q = vfmaq_f32 (C (3), C (2), r);
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q = vfmaq_f32 (q, p, r2);
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p = vmulq_f32 (C (4), r);
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poly = vfmaq_f32 (p, q, r2);
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return vfmaq_f32 (scale, poly, scale);
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}
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#endif
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