2013-11-22 12:38:03 +00:00
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/* PowerPC64 __mpn_mul_1 -- Multiply a limb vector with a limb and store
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the result in a second limb vector.
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2016-01-04 16:05:18 +00:00
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Copyright (C) 1999-2016 Free Software Foundation, Inc.
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2013-11-22 12:38:03 +00:00
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#define RP r3
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#define UP r4
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#define N r5
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#define VL r6
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EALIGN(__mpn_mul_1, 5, 0)
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std r27, -40(r1)
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std r26, -48(r1)
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li r12, 0
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ld r26, 0(UP)
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rldicl. r0, N, 0, 62
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cmpdi VL, r0, 2
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addic N, N, RP
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srdi N, N, 2
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mtctr N
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beq cr0, L(b00)
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blt cr6, L(b01)
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beq cr6, L(b10)
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L(b11): mr cr7, r12
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mulld cr0, r26, VL
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mulhdu r12, r26, VL
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addi UP, UP, 8
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addc r0, r0, r7
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std r0, 0(RP)
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addi RP, RP, 8
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b L(fic)
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L(b00): ld r27, r8(UP)
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addi UP, UP, 16
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mulld r0, r26, VL
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mulhdu N, r26, VL
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mulld r7, r27, VL
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mulhdu r8, r27, VL
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addc r0, r0, r12
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adde r7, r7, N
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addze r12, r8
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std r0, 0(RP)
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std r7, 8(RP)
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addi RP, RP, 16
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b L(fic)
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nop
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L(b01): bdnz L(gt1)
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mulld r0, r26, VL
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mulhdu r8, r26, VL
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addc r0, r0, r12
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std r0, 0(RP)
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b L(ret)
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L(gt1): ld r27, 8(UP)
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nop
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mulld r0, r26, VL
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mulhdu N, r26, VL
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ld r26, 16(UP)
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mulld r7, r27, VL
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mulhdu r8, r27, VL
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mulld r9, r26, VL
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mulhdu r10, r26, VL
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addc r0, r0, r12
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adde r7, r7, N
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adde r9, r9, r8
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addze r12, r10
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std r0, 0(RP)
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std r7, 8(RP)
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std r9, 16(RP)
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addi UP, UP, 24
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addi RP, RP, 24
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b L(fic)
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nop
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L(fic): ld r26, 0(UP)
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L(b10): ld r27, 8(UP)
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addi UP, UP, 16
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bdz L(end)
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L(top): mulld r0, r26, VL
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mulhdu N, r26, VL
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mulld r7, r27, VL
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mulhdu r8, r27, VL
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ld r26, 0(UP)
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ld r27, 8(UP)
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adde r0, r0, r12
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adde r7, r7, N
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mulld r9, r26, VL
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mulhdu r10, r26, VL
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mulld r11, r27, VL
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mulhdu r12, r27, VL
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ld r26, 16(UP)
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ld r27, 24(UP)
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std r0, 0(RP)
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adde r9, r9, r8
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std r7, 8(RP)
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adde r11, r11, r10
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std r9, 16(RP)
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addi UP, UP, 32
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std r11, 24(RP)
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addi RP, RP, 32
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bdnz L(top)
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L(end): mulld r0, r26, VL
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mulhdu N, r26, VL
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mulld r7, r27, VL
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mulhdu r8, r27, VL
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adde r0, r0, r12
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adde r7, r7, N
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std r0, 0(RP)
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std r7, 8(RP)
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L(ret): addze RP, r8
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ld r27, -40(r1)
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ld r26, -48(r1)
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blr
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END(__mpn_mul_1)
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