2024-05-08 02:06:15 +00:00
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/* Thread-local storage handling in the ELF dynamic linker.
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LoongArch version.
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Copyright (C) 2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include <tls.h>
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#include "tlsdesc.h"
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.text
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/* Compute the thread pointer offset for symbols in the static
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TLS block. The offset is the same for all threads.
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Prototype:
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_dl_tlsdesc_return (tlsdesc *); */
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.hidden _dl_tlsdesc_return
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.global _dl_tlsdesc_return
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.type _dl_tlsdesc_return,%function
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cfi_startproc
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.align 2
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_dl_tlsdesc_return:
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REG_L a0, a0, 8
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RET
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cfi_endproc
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.size _dl_tlsdesc_return, .-_dl_tlsdesc_return
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/* Handler for undefined weak TLS symbols.
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Prototype:
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_dl_tlsdesc_undefweak (tlsdesc *);
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The second word of the descriptor contains the addend.
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Return the addend minus the thread pointer. This ensures
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that when the caller adds on the thread pointer it gets back
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the addend. */
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.hidden _dl_tlsdesc_undefweak
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.global _dl_tlsdesc_undefweak
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.type _dl_tlsdesc_undefweak,%function
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cfi_startproc
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.align 2
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_dl_tlsdesc_undefweak:
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REG_L a0, a0, 8
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sub.d a0, a0, tp
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RET
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cfi_endproc
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.size _dl_tlsdesc_undefweak, .-_dl_tlsdesc_undefweak
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#ifdef SHARED
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#define FRAME_SIZE (-((-14 * SZREG) & ALMASK))
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#define FRAME_SIZE_LSX (-((-32 * SZVREG) & ALMASK))
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#define FRAME_SIZE_LASX (-((-32 * SZXREG) & ALMASK))
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#define FRAME_SIZE_FLOAT (-((-24 * SZFREG) & ALMASK))
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/* Handler for dynamic TLS symbols.
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Prototype:
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_dl_tlsdesc_dynamic (tlsdesc *) ;
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The second word of the descriptor points to a
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tlsdesc_dynamic_arg structure.
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Returns the offset between the thread pointer and the
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object referenced by the argument.
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ptrdiff_t
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_dl_tlsdesc_dynamic (struct tlsdesc *tdp)
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{
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struct tlsdesc_dynamic_arg *td = tdp->arg;
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dtv_t *dtv = *(dtv_t **)((char *)__thread_pointer - TCBHEAD_DTV);
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if (__glibc_likely (td->gen_count <= dtv[0].counter
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&& (dtv[td->tlsinfo.ti_module].pointer.val
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!= TLS_DTV_UNALLOCATED),
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1))
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return dtv[td->tlsinfo.ti_module].pointer.val
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+ td->tlsinfo.ti_offset
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- __thread_pointer;
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return ___tls_get_addr (&td->tlsinfo) - __thread_pointer;
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} */
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.hidden _dl_tlsdesc_dynamic
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.global _dl_tlsdesc_dynamic
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.type _dl_tlsdesc_dynamic,%function
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cfi_startproc
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.align 2
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_dl_tlsdesc_dynamic:
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/* Save just enough registers to support fast path, if we fall
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into slow path we will save additional registers. */
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ADDI sp, sp, -32
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2024-05-08 02:06:15 +00:00
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REG_S t0, sp, 0
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REG_S t1, sp, 8
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REG_S t2, sp, 16
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/* Runtime Storage Layout of Thread-Local Storage
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TP point to the start of TLS block.
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dtv
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Low address TCB ----------------> dtv0(counter)
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TP --> static_block0 <----- dtv1
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static_block1 <----- dtv2
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static_block2 <----- dtv3
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dynamic_block0 <----- dtv4
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Hign address dynamic_block1 <----- dtv5 */
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REG_L t0, tp, -SIZE_OF_TCB /* t0 = dtv */
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REG_L a0, a0, TLSDESC_ARG /* a0(td) = tdp->arg */
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REG_L t1, a0, TLSDESC_GEN_COUNT /* t1 = td->gen_count */
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REG_L t2, t0, DTV_COUNTER /* t2 = dtv[0].counter */
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/* If dtv[0].counter < td->gen_count, goto slow path. */
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bltu t2, t1, .Lslow
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REG_L t1, a0, TLSDESC_MODID /* t1 = td->tlsinfo.ti_module */
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/* t1 = t1 * sizeof(dtv_t) = t1 * (2 * sizeof(void*)) */
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slli.d t1, t1, 4
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add.d t1, t1, t0 /* t1 = dtv[td->tlsinfo.ti_module] */
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REG_L t1, t1, 0 /* t1 = dtv[td->tlsinfo.ti_module].pointer.val */
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li.d t2, TLS_DTV_UNALLOCATED
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/* If dtv[td->tlsinfo.ti_module].pointer.val is TLS_DTV_UNALLOCATED,
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goto slow path. */
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beq t1, t2, .Lslow
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REG_L t2, a0, TLSDESC_MODOFF /* t2 = td->tlsinfo.ti_offset */
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/* dtv[td->tlsinfo.ti_module].pointer.val + td->tlsinfo.ti_offset */
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add.d a0, t1, t2
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.Lret:
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sub.d a0, a0, tp
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REG_L t0, sp, 0
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REG_L t1, sp, 8
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REG_L t2, sp, 16
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ADDI sp, sp, 32
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RET
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.Lslow:
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/* This is the slow path. We need to call __tls_get_addr() which
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means we need to save and restore all the register that the
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callee will trash. */
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/* Save the remaining registers that we must treat as caller save. */
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ADDI sp, sp, -FRAME_SIZE
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REG_S ra, sp, 0 * SZREG
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REG_S a1, sp, 1 * SZREG
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REG_S a2, sp, 2 * SZREG
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REG_S a3, sp, 3 * SZREG
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REG_S a4, sp, 4 * SZREG
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REG_S a5, sp, 5 * SZREG
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REG_S a6, sp, 6 * SZREG
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REG_S a7, sp, 7 * SZREG
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REG_S t3, sp, 8 * SZREG
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REG_S t4, sp, 9 * SZREG
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REG_S t5, sp, 10 * SZREG
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REG_S t6, sp, 11 * SZREG
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REG_S t7, sp, 12 * SZREG
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REG_S t8, sp, 13 * SZREG
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#ifndef __loongarch_soft_float
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/* Save fcsr0 register.
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Only one physical fcsr0 register, fcsr1-fcsr3 are aliases
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of some fields in fcsr0. */
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movfcsr2gr t0, fcsr0
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st.w t0, sp, FRAME_SIZE + 24 /* Use the spare slot above t2 */
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/* Whether support LASX. */
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la.global t0, _rtld_global_ro
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REG_L t0, t0, GLRO_DL_HWCAP_OFFSET
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andi t0, t0, HWCAP_LOONGARCH_LASX
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beqz t0, .Llsx
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/* Save 256-bit vector registers.
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FIXME: Without vector ABI, save all vector registers. */
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ADDI sp, sp, -FRAME_SIZE_LASX
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xvst xr0, sp, 0*SZXREG
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xvst xr1, sp, 1*SZXREG
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xvst xr2, sp, 2*SZXREG
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xvst xr3, sp, 3*SZXREG
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xvst xr4, sp, 4*SZXREG
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xvst xr5, sp, 5*SZXREG
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xvst xr6, sp, 6*SZXREG
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xvst xr7, sp, 7*SZXREG
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xvst xr8, sp, 8*SZXREG
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xvst xr9, sp, 9*SZXREG
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xvst xr10, sp, 10*SZXREG
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xvst xr11, sp, 11*SZXREG
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xvst xr12, sp, 12*SZXREG
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xvst xr13, sp, 13*SZXREG
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xvst xr14, sp, 14*SZXREG
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xvst xr15, sp, 15*SZXREG
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xvst xr16, sp, 16*SZXREG
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xvst xr17, sp, 17*SZXREG
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xvst xr18, sp, 18*SZXREG
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xvst xr19, sp, 19*SZXREG
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xvst xr20, sp, 20*SZXREG
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xvst xr21, sp, 21*SZXREG
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xvst xr22, sp, 22*SZXREG
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xvst xr23, sp, 23*SZXREG
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xvst xr24, sp, 24*SZXREG
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xvst xr25, sp, 25*SZXREG
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xvst xr26, sp, 26*SZXREG
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xvst xr27, sp, 27*SZXREG
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xvst xr28, sp, 28*SZXREG
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xvst xr29, sp, 29*SZXREG
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xvst xr30, sp, 30*SZXREG
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xvst xr31, sp, 31*SZXREG
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b .Ltga
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.Llsx:
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/* Whether support LSX. */
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andi t0, t0, HWCAP_LOONGARCH_LSX
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beqz t0, .Lfloat
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/* Save 128-bit vector registers. */
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ADDI sp, sp, -FRAME_SIZE_LSX
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vst vr0, sp, 0*SZVREG
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vst vr1, sp, 1*SZVREG
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vst vr2, sp, 2*SZVREG
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vst vr3, sp, 3*SZVREG
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vst vr4, sp, 4*SZVREG
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vst vr5, sp, 5*SZVREG
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vst vr6, sp, 6*SZVREG
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vst vr7, sp, 7*SZVREG
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vst vr8, sp, 8*SZVREG
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vst vr9, sp, 9*SZVREG
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vst vr10, sp, 10*SZVREG
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vst vr11, sp, 11*SZVREG
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vst vr12, sp, 12*SZVREG
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vst vr13, sp, 13*SZVREG
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vst vr14, sp, 14*SZVREG
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vst vr15, sp, 15*SZVREG
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vst vr16, sp, 16*SZVREG
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vst vr17, sp, 17*SZVREG
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vst vr18, sp, 18*SZVREG
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vst vr19, sp, 19*SZVREG
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vst vr20, sp, 20*SZVREG
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vst vr21, sp, 21*SZVREG
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vst vr22, sp, 22*SZVREG
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vst vr23, sp, 23*SZVREG
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vst vr24, sp, 24*SZVREG
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vst vr25, sp, 25*SZVREG
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vst vr26, sp, 26*SZVREG
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vst vr27, sp, 27*SZVREG
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vst vr28, sp, 28*SZVREG
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vst vr29, sp, 29*SZVREG
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vst vr30, sp, 30*SZVREG
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vst vr31, sp, 31*SZVREG
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b .Ltga
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.Lfloat:
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/* Save float registers. */
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ADDI sp, sp, -FRAME_SIZE_FLOAT
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FREG_S fa0, sp, 0*SZFREG
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FREG_S fa1, sp, 1*SZFREG
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FREG_S fa2, sp, 2*SZFREG
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FREG_S fa3, sp, 3*SZFREG
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FREG_S fa4, sp, 4*SZFREG
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FREG_S fa5, sp, 5*SZFREG
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FREG_S fa6, sp, 6*SZFREG
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FREG_S fa7, sp, 7*SZFREG
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FREG_S ft0, sp, 8*SZFREG
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FREG_S ft1, sp, 9*SZFREG
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FREG_S ft2, sp, 10*SZFREG
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FREG_S ft3, sp, 11*SZFREG
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FREG_S ft4, sp, 12*SZFREG
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FREG_S ft5, sp, 13*SZFREG
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FREG_S ft6, sp, 14*SZFREG
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FREG_S ft7, sp, 15*SZFREG
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FREG_S ft8, sp, 16*SZFREG
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FREG_S ft9, sp, 17*SZFREG
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FREG_S ft10, sp, 18*SZFREG
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FREG_S ft11, sp, 19*SZFREG
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FREG_S ft12, sp, 20*SZFREG
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FREG_S ft13, sp, 21*SZFREG
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FREG_S ft14, sp, 22*SZFREG
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FREG_S ft15, sp, 23*SZFREG
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#endif /* #ifndef __loongarch_soft_float */
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.Ltga:
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bl HIDDEN_JUMPTARGET(__tls_get_addr)
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ADDI a0, a0, -TLS_DTV_OFFSET
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#ifndef __loongarch_soft_float
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la.global t0, _rtld_global_ro
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REG_L t0, t0, GLRO_DL_HWCAP_OFFSET
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andi t0, t0, HWCAP_LOONGARCH_LASX
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beqz t0, .Llsx1
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/* Restore 256-bit vector registers. */
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xvld xr0, sp, 0*SZXREG
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xvld xr1, sp, 1*SZXREG
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xvld xr2, sp, 2*SZXREG
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xvld xr3, sp, 3*SZXREG
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xvld xr4, sp, 4*SZXREG
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xvld xr5, sp, 5*SZXREG
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xvld xr6, sp, 6*SZXREG
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xvld xr7, sp, 7*SZXREG
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xvld xr8, sp, 8*SZXREG
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xvld xr9, sp, 9*SZXREG
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xvld xr10, sp, 10*SZXREG
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xvld xr11, sp, 11*SZXREG
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xvld xr12, sp, 12*SZXREG
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xvld xr13, sp, 13*SZXREG
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xvld xr14, sp, 14*SZXREG
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xvld xr15, sp, 15*SZXREG
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xvld xr16, sp, 16*SZXREG
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xvld xr17, sp, 17*SZXREG
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xvld xr18, sp, 18*SZXREG
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xvld xr19, sp, 19*SZXREG
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xvld xr20, sp, 20*SZXREG
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xvld xr21, sp, 21*SZXREG
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xvld xr22, sp, 22*SZXREG
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xvld xr23, sp, 23*SZXREG
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xvld xr24, sp, 24*SZXREG
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xvld xr25, sp, 25*SZXREG
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xvld xr26, sp, 26*SZXREG
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xvld xr27, sp, 27*SZXREG
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xvld xr28, sp, 28*SZXREG
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xvld xr29, sp, 29*SZXREG
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xvld xr30, sp, 30*SZXREG
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xvld xr31, sp, 31*SZXREG
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ADDI sp, sp, FRAME_SIZE_LASX
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b .Lfcsr
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.Llsx1:
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andi t0, s0, HWCAP_LOONGARCH_LSX
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beqz t0, .Lfloat1
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/* Restore 128-bit vector registers. */
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vld vr0, sp, 0*SZVREG
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vld vr1, sp, 1*SZVREG
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vld vr2, sp, 2*SZVREG
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vld vr3, sp, 3*SZVREG
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vld vr4, sp, 4*SZVREG
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vld vr5, sp, 5*SZVREG
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vld vr6, sp, 6*SZVREG
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vld vr7, sp, 7*SZVREG
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vld vr8, sp, 8*SZVREG
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vld vr9, sp, 9*SZVREG
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vld vr10, sp, 10*SZVREG
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vld vr11, sp, 11*SZVREG
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vld vr12, sp, 12*SZVREG
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vld vr13, sp, 13*SZVREG
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vld vr14, sp, 14*SZVREG
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vld vr15, sp, 15*SZVREG
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vld vr16, sp, 16*SZVREG
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vld vr17, sp, 17*SZVREG
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vld vr18, sp, 18*SZVREG
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vld vr19, sp, 19*SZVREG
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vld vr20, sp, 20*SZVREG
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vld vr21, sp, 21*SZVREG
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vld vr22, sp, 22*SZVREG
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vld vr23, sp, 23*SZVREG
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vld vr24, sp, 24*SZVREG
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vld vr25, sp, 25*SZVREG
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vld vr26, sp, 26*SZVREG
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vld vr27, sp, 27*SZVREG
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vld vr28, sp, 28*SZVREG
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vld vr29, sp, 29*SZVREG
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vld vr30, sp, 30*SZVREG
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vld vr31, sp, 31*SZVREG
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ADDI sp, sp, FRAME_SIZE_LSX
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b .Lfcsr
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.Lfloat1:
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/* Restore float registers. */
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FREG_L fa0, sp, 0*SZFREG
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FREG_L fa1, sp, 1*SZFREG
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FREG_L fa2, sp, 2*SZFREG
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FREG_L fa3, sp, 3*SZFREG
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FREG_L fa4, sp, 4*SZFREG
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FREG_L fa5, sp, 5*SZFREG
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FREG_L fa6, sp, 6*SZFREG
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FREG_L fa7, sp, 7*SZFREG
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FREG_L ft0, sp, 8*SZFREG
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FREG_L ft1, sp, 9*SZFREG
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FREG_L ft2, sp, 10*SZFREG
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FREG_L ft3, sp, 11*SZFREG
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FREG_L ft4, sp, 12*SZFREG
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FREG_L ft5, sp, 13*SZFREG
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FREG_L ft6, sp, 14*SZFREG
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FREG_L ft7, sp, 15*SZFREG
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FREG_L ft8, sp, 16*SZFREG
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FREG_L ft9, sp, 17*SZFREG
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FREG_L ft10, sp, 18*SZFREG
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FREG_L ft11, sp, 19*SZFREG
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FREG_L ft12, sp, 20*SZFREG
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FREG_L ft13, sp, 21*SZFREG
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FREG_L ft14, sp, 22*SZFREG
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FREG_L ft15, sp, 23*SZFREG
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ADDI sp, sp, FRAME_SIZE_FLOAT
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.Lfcsr:
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/* Restore fcsr0 register. */
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2024-06-13 11:04:05 +00:00
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ld.w t0, sp, FRAME_SIZE + 24
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2024-05-08 02:06:15 +00:00
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movgr2fcsr fcsr0, t0
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#endif /* #ifndef __loongarch_soft_float */
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REG_L ra, sp, 0 * SZREG
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REG_L a1, sp, 1 * SZREG
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REG_L a2, sp, 2 * SZREG
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REG_L a3, sp, 3 * SZREG
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REG_L a4, sp, 4 * SZREG
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REG_L a5, sp, 5 * SZREG
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REG_L a6, sp, 6 * SZREG
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REG_L a7, sp, 7 * SZREG
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REG_L t3, sp, 8 * SZREG
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REG_L t4, sp, 9 * SZREG
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REG_L t5, sp, 10 * SZREG
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REG_L t6, sp, 11 * SZREG
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REG_L t7, sp, 12 * SZREG
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REG_L t8, sp, 13 * SZREG
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ADDI sp, sp, FRAME_SIZE
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b .Lret
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cfi_endproc
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.size _dl_tlsdesc_dynamic, .-_dl_tlsdesc_dynamic
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.hidden HIDDEN_JUMPTARGET(__tls_get_addr)
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#endif /* #ifdef SHARED */
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