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50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
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#define _FP_W_TYPE_SIZE 64
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#define _FP_W_TYPE unsigned long
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#define _FP_WS_TYPE signed long
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#define _FP_I_TYPE long
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#define __FP_CLZ(r, x) \
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do { \
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__asm__("bsrq %1,%0" : "=r"(r) : "g"(x) : "cc"); \
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r ^= 63; \
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} while (0)
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#define _FP_NANFRAC_S _FP_QNANBIT_S
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#define _FP_NANFRAC_D _FP_QNANBIT_D, 0
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#define _FP_NANSIGN_S 1
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#define _FP_NANSIGN_D 1
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#define _FP_KEEPNANFRACP 1
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/* Here is something Intel misdesigned: the specs don't define
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the case where we have two NaNs with same mantissas, but
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different sign. Different operations pick up different NaNs.
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*/
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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if (_FP_FRAC_GT_##wc(X, Y) \
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|| (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
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{ \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R,X); \
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} \
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else \
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{ \
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R##_s = Y##_s; \
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_FP_FRAC_COPY_##wc(R,Y); \
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} \
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R##_c = FP_CLS_NAN; \
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} while (0)
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#define FP_EX_INVALID (1 << 0)
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#define FP_EX_DENORM (1 << 1)
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#define FP_EX_DIVZERO (1 << 2)
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#define FP_EX_OVERFLOW (1 << 3)
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#define FP_EX_UNDERFLOW (1 << 4)
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#define FP_EX_INEXACT (1 << 5)
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#define FP_RND_NEAREST 0
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#define FP_RND_ZERO 3
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#define FP_RND_PINF 2
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#define FP_RND_MINF 1
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