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67 lines
2.1 KiB
C
67 lines
2.1 KiB
C
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/* Copyright (C) 1994 Free Software Foundation, Inc.
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Contributed by Joel Sherrill (jsherril@redstone-emh2.army.mil),
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On-Line Applications Research Corporation.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Library General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Library General Public License for more details.
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You should have received a copy of the GNU Library General Public
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License along with the GNU C Library; see the file COPYING.LIB. If
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not, write to the Free Software Foundation, Inc., 675 Mass Ave,
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Cambridge, MA 02139, USA. */
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#include <ansidecl.h>
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#include <standalone.h>
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#include "i960ca.h"
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/* _Board_Initialize()
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This routine initializes the board.
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NOTE: Only tested on a Cyclone CVME961 but should be OK on any i960ca board. */
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void
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DEFUN_VOID(_Board_Initialize)
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{
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struct i80960ca_prcb *prcb; /* ptr to processor control block */
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struct i80960ca_ctltbl *ctl_tbl; /* ptr to control table */
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static inline struct i80960ca_prcb *get_prcb()
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{ register struct i80960ca_prcb *_prcb = 0;
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asm volatile( "calls 5; \
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mov g0,%0" \
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: "=d" (_prcb) \
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: "0" (_prcb) );
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return ( _prcb );
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}
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prcb = get_prcb();
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ctl_tbl = prcb->control_tbl;
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/* The following configures the data breakpoint (which must be set
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* before this is executed) to break on writes only.
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*/
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ctl_tbl->bpcon &= ~0x00cc0000;
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reload_ctl_group( 6 );
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/* bit 31 of the Register Cache Control can be set to
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* enable an alternative caching algorithm. It does
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* not appear to help our applications.
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*/
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/* Configure Number of Register Caches */
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prcb->reg_cache_cfg = 8;
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soft_reset( prcb );
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}
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