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x86: Fix misordered logic for setting rep_movsb_stop_threshold
Move the setting of `rep_movsb_stop_threshold` to after the tunables have been collected so that the `rep_movsb_stop_threshold` (which is used to redirect control flow to the non_temporal case) will use any user value for `non_temporal_threshold` (set using glibc.cpu.x86_non_temporal_threshold)
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@ -898,18 +898,6 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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if (CPU_FEATURE_USABLE_P (cpu_features, FSRM))
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rep_movsb_threshold = 2112;
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unsigned long int rep_movsb_stop_threshold;
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/* ERMS feature is implemented from AMD Zen3 architecture and it is
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performing poorly for data above L2 cache size. Henceforth, adding
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an upper bound threshold parameter to limit the usage of Enhanced
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REP MOVSB operations and setting its value to L2 cache size. */
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if (cpu_features->basic.kind == arch_kind_amd)
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rep_movsb_stop_threshold = core;
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/* Setting the upper bound of ERMS to the computed value of
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non-temporal threshold for architectures other than AMD. */
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else
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rep_movsb_stop_threshold = non_temporal_threshold;
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/* The default threshold to use Enhanced REP STOSB. */
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unsigned long int rep_stosb_threshold = 2048;
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@ -951,6 +939,18 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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SIZE_MAX);
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#endif
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unsigned long int rep_movsb_stop_threshold;
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/* ERMS feature is implemented from AMD Zen3 architecture and it is
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performing poorly for data above L2 cache size. Henceforth, adding
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an upper bound threshold parameter to limit the usage of Enhanced
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REP MOVSB operations and setting its value to L2 cache size. */
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if (cpu_features->basic.kind == arch_kind_amd)
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rep_movsb_stop_threshold = core;
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/* Setting the upper bound of ERMS to the computed value of
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non-temporal threshold for architectures other than AMD. */
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else
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rep_movsb_stop_threshold = non_temporal_threshold;
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cpu_features->data_cache_size = data;
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cpu_features->shared_cache_size = shared;
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cpu_features->non_temporal_threshold = non_temporal_threshold;
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