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Make armv7 strcmp assembly compatible with ARM mode and SFI.
This commit is contained in:
Roland McGrath
parent
0ded08a566
commit
0a982a2905
@ -1,3 +1,8 @@
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2014-05-09 Roland McGrath <roland@hack.frob.com>
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* sysdeps/arm/armv7/strcmp.S: Use sfi_breg prefix on loads not from sp.
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[NO_THUMB]: Cope without cbz, cnbz, and orn instructions.
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2014-05-09 Adhemerval Zanella <azanella@linux.vnet.ibm.com>
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* elf/Makefile (tst-tlsmod5.so): Add $(no-as-needed).
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@ -35,8 +35,6 @@
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#define STRCMP_PRECHECK 1
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/* This version uses Thumb-2 code. */
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.thumb
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.syntax unified
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#ifdef __ARM_BIG_ENDIAN
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@ -85,6 +83,39 @@
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#define syndrome tmp2
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#ifndef NO_THUMB
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/* This code is best on Thumb. */
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.thumb
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/* In Thumb code we can't use MVN with a register shift, but we do have ORN. */
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.macro prepare_mask mask_reg, nbits_reg
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S2HI \mask_reg, const_m1, \nbits_reg
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.endm
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.macro apply_mask data_reg, mask_reg
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orn \data_reg, \data_reg, \mask_reg
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.endm
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#else
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/* In ARM code we don't have ORN, but we can use MVN with a register shift. */
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.macro prepare_mask mask_reg, nbits_reg
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mvn \mask_reg, const_m1, S2HI \nbits_reg
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.endm
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.macro apply_mask data_reg, mask_reg
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orr \data_reg, \data_reg, \mask_reg
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.endm
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/* These clobber the condition codes, which the real Thumb cbz/cbnz
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instructions do not. But it doesn't matter for any of the uses here. */
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.macro cbz reg, label
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cmp \reg, #0
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beq \label
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.endm
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.macro cbnz reg, label
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cmp \reg, #0
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bne \label
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.endm
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#endif
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/* Macro to compute and return the result value for word-aligned
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cases. */
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.macro strcmp_epilogue_aligned synd d1 d2 restore_r6
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@ -147,8 +178,10 @@
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#endif
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ENTRY (strcmp)
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#if STRCMP_PRECHECK == 1
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ldrb r2, [src1]
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ldrb r3, [src2]
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sfi_breg src1, \
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ldrb r2, [\B]
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sfi_breg src2, \
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ldrb r3, [\B]
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cmp r2, #1
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it cs
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cmpcs r2, r3
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@ -178,18 +211,18 @@ ENTRY (strcmp)
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and tmp2, tmp1, #3
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bic src2, src2, #7
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lsl tmp2, tmp2, #3 /* Bytes -> bits. */
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ldrd data1a, data1b, [src1], #16
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sfi_breg src1, \
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ldrd data1a, data1b, [\B], #16
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tst tmp1, #4
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ldrd data2a, data2b, [src2], #16
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/* In thumb code we can't use MVN with a register shift, but
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we do have ORN. */
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S2HI tmp1, const_m1, tmp2
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orn data1a, data1a, tmp1
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orn data2a, data2a, tmp1
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sfi_breg src2, \
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ldrd data2a, data2b, [\B], #16
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prepare_mask tmp1, tmp2
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apply_mask data1a, tmp1
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apply_mask data2a, tmp1
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beq .Lstart_realigned8
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orn data1b, data1b, tmp1
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apply_mask data1b, tmp1
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mov data1a, const_m1
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orn data2b, data2b, tmp1
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apply_mask data2b, tmp1
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mov data2a, const_m1
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b .Lstart_realigned8
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@ -198,8 +231,10 @@ ENTRY (strcmp)
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.p2align 5,,12 /* Don't start in the tail bytes of a cache line. */
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.p2align 2 /* Always word aligned. */
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.Lloop_aligned8:
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ldrd data1a, data1b, [src1], #16
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ldrd data2a, data2b, [src2], #16
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sfi_breg src1, \
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ldrd data1a, data1b, [\B], #16
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sfi_breg src2, \
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ldrd data2a, data2b, [\B], #16
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.Lstart_realigned8:
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uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */
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eor syndrome_a, data1a, data2a
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@ -210,8 +245,10 @@ ENTRY (strcmp)
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sel syndrome_b, syndrome_b, const_m1
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cbnz syndrome_b, .Ldiff_in_b
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ldrd data1a, data1b, [src1, #-8]
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ldrd data2a, data2b, [src2, #-8]
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sfi_breg src1, \
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ldrd data1a, data1b, [\B, #-8]
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sfi_breg src2, \
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ldrd data2a, data2b, [\B, #-8]
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uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */
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eor syndrome_a, data1a, data2a
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sel syndrome_a, syndrome_a, const_m1
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@ -242,15 +279,19 @@ ENTRY (strcmp)
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/* Unrolled by a factor of 2, to reduce the number of post-increment
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operations. */
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.Lloop_aligned4:
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ldr data1, [src1], #8
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ldr data2, [src2], #8
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sfi_breg src1, \
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ldr data1, [\B], #8
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sfi_breg src2, \
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ldr data2, [\B], #8
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.Lstart_realigned4:
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uadd8 syndrome, data1, const_m1 /* Only need GE bits. */
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eor syndrome, data1, data2
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sel syndrome, syndrome, const_m1
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cbnz syndrome, .Laligned4_done
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ldr data1, [src1, #-4]
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ldr data2, [src2, #-4]
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sfi_breg src1, \
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ldr data1, [\B, #-4]
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sfi_breg src2, \
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ldr data2, [\B, #-4]
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uadd8 syndrome, data1, const_m1
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eor syndrome, data1, data2
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sel syndrome, syndrome, const_m1
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@ -266,15 +307,15 @@ ENTRY (strcmp)
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masking off the unwanted loaded data to prevent a difference. */
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lsl tmp1, tmp1, #3 /* Bytes -> bits. */
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bic src1, src1, #3
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ldr data1, [src1], #8
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sfi_breg src1, \
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ldr data1, [\B], #8
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bic src2, src2, #3
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ldr data2, [src2], #8
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sfi_breg src2, \
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ldr data2, [\B], #8
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/* In thumb code we can't use MVN with a register shift, but
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we do have ORN. */
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S2HI tmp1, const_m1, tmp1
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orn data1, data1, tmp1
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orn data2, data2, tmp1
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prepare_mask tmp1, tmp1
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apply_mask data1, tmp1
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apply_mask data2, tmp1
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b .Lstart_realigned4
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.Lmisaligned4:
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@ -283,26 +324,30 @@ ENTRY (strcmp)
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sub src2, src2, tmp1
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bic src1, src1, #3
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lsls tmp1, tmp1, #31
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ldr data1, [src1], #4
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sfi_breg src1, \
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ldr data1, [\B], #4
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beq .Laligned_m2
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bcs .Laligned_m1
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#if STRCMP_PRECHECK == 0
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ldrb data2, [src2, #1]
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sfi_breg src2, \
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ldrb data2, [\B, #1]
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uxtb tmp1, data1, ror #BYTE1_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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cbz data2, .Lmisaligned_exit
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.Laligned_m2:
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ldrb data2, [src2, #2]
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sfi_breg src2, \
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ldrb data2, [\B, #2]
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uxtb tmp1, data1, ror #BYTE2_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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cbz data2, .Lmisaligned_exit
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.Laligned_m1:
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ldrb data2, [src2, #3]
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sfi_breg src2, \
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ldrb data2, [\B, #3]
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uxtb tmp1, data1, ror #BYTE3_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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@ -311,14 +356,16 @@ ENTRY (strcmp)
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#else /* STRCMP_PRECHECK */
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/* If we've done the pre-check, then we don't need to check the
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first byte again here. */
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ldrb data2, [src2, #2]
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sfi_breg src2, \
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ldrb data2, [\B, #2]
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uxtb tmp1, data1, ror #BYTE2_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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cbz data2, .Lmisaligned_exit
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.Laligned_m2:
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ldrb data2, [src2, #3]
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sfi_breg src2, \
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ldrb data2, [\B, #3]
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uxtb tmp1, data1, ror #BYTE3_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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@ -344,11 +391,13 @@ ENTRY (strcmp)
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cfi_restore_state
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/* src1 is word aligned, but src2 has no common alignment
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with it. */
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ldr data1, [src1], #4
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sfi_breg src1, \
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ldr data1, [\B], #4
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lsls tmp1, src2, #31 /* C=src2[1], Z=src2[0]. */
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bic src2, src2, #3
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ldr data2, [src2], #4
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sfi_breg src2, \
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ldr data2, [\B], #4
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bhi .Loverlap1 /* C=1, Z=0 => src2[1:0] = 0b11. */
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bcs .Loverlap2 /* C=1, Z=1 => src2[1:0] = 0b10. */
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@ -360,11 +409,13 @@ ENTRY (strcmp)
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sel syndrome, syndrome, const_m1
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bne 4f
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cbnz syndrome, 5f
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ldr data2, [src2], #4
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sfi_breg src2, \
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ldr data2, [\B], #4
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eor tmp1, tmp1, data1
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cmp tmp1, data2, S2HI #24
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bne 6f
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ldr data1, [src1], #4
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sfi_breg src1, \
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ldr data1, [\B], #4
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b .Loverlap3
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4:
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S2LO data2, data2, #8
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@ -376,7 +427,8 @@ ENTRY (strcmp)
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/* We can only get here if the MSB of data1 contains 0, so
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fast-path the exit. */
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ldrb result, [src2]
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sfi_breg src2, \
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ldrb result, [\B]
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ldrd r4, r5, [sp], #16
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cfi_remember_state
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cfi_def_cfa_offset (0)
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@ -402,11 +454,13 @@ ENTRY (strcmp)
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sel syndrome, syndrome, const_m1
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bne 4f
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cbnz syndrome, 5f
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ldr data2, [src2], #4
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sfi_breg src2, \
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ldr data2, [\B], #4
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eor tmp1, tmp1, data1
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cmp tmp1, data2, S2HI #16
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bne 6f
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ldr data1, [src1], #4
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sfi_breg src1, \
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ldr data1, [\B], #4
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b .Loverlap2
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4:
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S2LO data2, data2, #16
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@ -415,7 +469,8 @@ ENTRY (strcmp)
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ands syndrome, syndrome, const_m1, S2LO #16
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bne .Lstrcmp_done_equal
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ldrh data2, [src2]
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sfi_breg src2, \
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ldrh data2, [\B]
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S2LO data1, data1, #16
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#ifdef __ARM_BIG_ENDIAN
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lsl data2, data2, #16
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@ -435,11 +490,13 @@ ENTRY (strcmp)
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sel syndrome, syndrome, const_m1
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bne 4f
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cbnz syndrome, 5f
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ldr data2, [src2], #4
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sfi_breg src2, \
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ldr data2, [\B], #4
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eor tmp1, tmp1, data1
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cmp tmp1, data2, S2HI #8
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bne 6f
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ldr data1, [src1], #4
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sfi_breg src1, \
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ldr data1, [\B], #4
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b .Loverlap1
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4:
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S2LO data2, data2, #24
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@ -447,7 +504,8 @@ ENTRY (strcmp)
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5:
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tst syndrome, #LSB
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bne .Lstrcmp_done_equal
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ldr data2, [src2]
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sfi_breg src2, \
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ldr data2, [\B]
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6:
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S2LO data1, data1, #8
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bic data2, data2, #MSB
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