AuroraMiddleware/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2024-11-21 20:40:05 +00:00
Code Issues Packages Projects Releases Wiki Activity

Initial Fast Short REP MOVSB (FSRM) support

Browse Source 
The newer Intel processors support Fast Short REP MOVSB which has a
feature bit in CPUID.  This patch adds the Fast Short REP MOVSB (FSRM)
bit to x86 cpu-features.

	* sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New.
	(index_cpu_FSRM): Likewise.
	(reg_FSRM): Likewise.
This commit is contained in:
H.J. Lu 2018-05-21 10:54:20 -07:00
parent 7c67e6e8b9
commit 1af30adcd5
2 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ChangeLog
View File

@ -1,3 +1,9 @@
2018-05-21 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New.
(index_cpu_FSRM): Likewise.
(reg_FSRM): Likewise.
2018-05-18 Joseph Myers <joseph@codesourcery.com>
* math/gen-tgmath-tests.py: Import sys.

3
sysdeps/x86/cpu-features.h
View File

@ -76,6 +76,7 @@
#define bit_cpu_AVX512VL (1u << 31)
#define bit_cpu_IBT (1u << 20)
#define bit_cpu_SHSTK (1u << 7)
#define bit_cpu_FSRM (1 << 4)
/* XCR0 Feature flags. */
#define bit_XMM_state (1 << 1)
@ -207,6 +208,7 @@ extern const struct cpu_features *__get_cpu_features (void)
# define index_cpu_POPCNT COMMON_CPUID_INDEX_1
# define index_cpu_IBT COMMON_CPUID_INDEX_7
# define index_cpu_SHSTK COMMON_CPUID_INDEX_7
# define index_cpu_FSRM COMMON_CPUID_INDEX_7
# define reg_CX8 edx
# define reg_CMOV edx
@ -238,6 +240,7 @@ extern const struct cpu_features *__get_cpu_features (void)
# define reg_POPCNT ecx
# define reg_IBT edx
# define reg_SHSTK ecx
# define reg_FSRM edx
# define index_arch_Fast_Rep_String FEATURE_INDEX_1
# define index_arch_Fast_Copy_Backward FEATURE_INDEX_1