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Define bit_SSE2 and index_SSE2.

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H.J. Lu 2009-12-13 15:23:02 -08:00 committed by Ulrich Drepper
parent 23b8575625
commit 2510d01ddb
5 changed files with 20 additions and 8 deletions
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10
ChangeLog
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@ -1,3 +1,13 @@
2009-12-13 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/i386/i686/multiarch/strcspn.S Include <init-arch.h>
instead of <ifunc-defines.h>. Use bit_XXX and index_XXX to
check processor feature.
* sysdeps/i386/i686/multiarch/strlen.S: Likewise.
* sysdeps/i386/i686/multiarch/strspn.S: Likewise.
* sysdeps/x86_64/multiarch/init-arch.h (bit_SSE2): New definition.
(index_SSE2): Likewise.
2009-12-09 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86_64/multiarch/init-arch.h: Include <ifunc-defines.h>

6
sysdeps/i386/i686/multiarch/strcspn.S
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@ -23,7 +23,7 @@
#ifdef HAVE_SSE4_SUPPORT
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
#ifdef USE_AS_STRPBRK
#define STRCSPN_SSE42 __strpbrk_sse42
@ -64,7 +64,7 @@ ENTRY(STRCSPN)
jne 1f
call __init_cpu_features
1: leal STRCSPN_IA32@GOTOFF(%ebx), %eax
testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx)
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f
leal STRCSPN_SSE42@GOTOFF(%ebx), %eax
2: popl %ebx
@ -80,7 +80,7 @@ ENTRY(STRCSPN)
jne 1f
call __init_cpu_features
1: leal STRCSPN_IA32, %eax
testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
leal STRCSPN_SSE42, %eax
2: ret

4
sysdeps/i386/i686/multiarch/strlen.S
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@ -19,7 +19,7 @@
02111-1307 USA. */
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
/* Define multiple versions only for the definition in libc and for the
DSO. In static binaries, we need strlen before the initialization
@ -46,7 +46,7 @@ ENTRY(strlen)
jne 1f
call __init_cpu_features
1: leal __strlen_ia32@GOTOFF(%ebx), %eax
testl $(1<<26), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET+__cpu_features@GOTOFF(%ebx)
testl $bit_SSE2, CPUID_OFFSET+index_SSE2+__cpu_features@GOTOFF(%ebx)
jz 2f
leal __strlen_sse2@GOTOFF(%ebx), %eax
2: popl %ebx

6
sysdeps/i386/i686/multiarch/strspn.S
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@ -23,7 +23,7 @@
#ifdef HAVE_SSE4_SUPPORT
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
/* Define multiple versions only for the definition in libc. */
#ifndef NOT_IN_libc
@ -49,7 +49,7 @@ ENTRY(strspn)
jne 1f
call __init_cpu_features
1: leal __strspn_ia32@GOTOFF(%ebx), %eax
testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx)
testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx)
jz 2f
leal __strspn_sse42@GOTOFF(%ebx), %eax
2: popl %ebx
@ -65,7 +65,7 @@ ENTRY(strspn)
jne 1f
call __init_cpu_features
1: leal __strspn_ia32, %eax
testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features
testl $index_SSE2, CPUID_OFFSET+index_SSE4_2+__cpu_features
jz 2f
leal __strspn_sse42, %eax
2: ret

2
sysdeps/x86_64/multiarch/init-arch.h
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@ -20,9 +20,11 @@
#include <ifunc-defines.h>
#define bit_SSE2 (1 << 26)
#define bit_SSSE3 (1 << 9)
#define bit_SSE4_2 (1 << 20)
#define index_SSE2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
#define index_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
#define index_SSE4_2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET