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x86: Use VMM API in memcmpeq-evex.S and minor changes
Changes to generated code are:
1. In a few places use `vpcmpeqb` instead of `vpcmpneq` to save a
byte of code size.
2. Add a branch for length <= (VEC_SIZE * 6) as opposed to doing
the entire block of [VEC_SIZE * 4 + 1, VEC_SIZE * 8] in a
single basic-block (the space to add the extra branch without
changing code size is bought with the above change).
Change (2) has roughly a 20-25% speedup for sizes in [VEC_SIZE * 4 +
1, VEC_SIZE * 6] and negligible to no-cost for [VEC_SIZE * 6 + 1,
VEC_SIZE * 8]
From N=10 runs on Tigerlake:
align1,align2 ,length ,result ,New Time ,Cur Time ,New Time / Old Time
0 ,0 ,129 ,0 ,5.404 ,6.887 ,0.785
0 ,0 ,129 ,1 ,5.308 ,6.826 ,0.778
0 ,0 ,129 ,18446744073709551615 ,5.359 ,6.823 ,0.785
0 ,0 ,161 ,0 ,5.284 ,6.827 ,0.774
0 ,0 ,161 ,1 ,5.317 ,6.745 ,0.788
0 ,0 ,161 ,18446744073709551615 ,5.406 ,6.778 ,0.798
0 ,0 ,193 ,0 ,6.804 ,6.802 ,1.000
0 ,0 ,193 ,1 ,6.950 ,6.754 ,1.029
0 ,0 ,193 ,18446744073709551615 ,6.792 ,6.719 ,1.011
0 ,0 ,225 ,0 ,6.625 ,6.699 ,0.989
0 ,0 ,225 ,1 ,6.776 ,6.735 ,1.003
0 ,0 ,225 ,18446744073709551615 ,6.758 ,6.738 ,0.992
0 ,0 ,256 ,0 ,5.402 ,5.462 ,0.989
0 ,0 ,256 ,1 ,5.364 ,5.483 ,0.978
0 ,0 ,256 ,18446744073709551615 ,5.341 ,5.539 ,0.964
Rewriting with VMM API allows for memcmpeq-evex to be used with
evex512 by including "x86-evex512-vecs.h" at the top.
Complete check passes on x86-64.
This commit is contained in:
Noah Goldstein
parent
419c832aba
commit
2d2493a644
@ -41,24 +41,53 @@
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# define MEMCMPEQ __memcmpeq_evex
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# endif
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# ifndef VEC_SIZE
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# include "x86-evex512-vecs.h"
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# endif
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# include "reg-macros.h"
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# if VEC_SIZE == 32
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# define TEST_ZERO_VCMP(reg) inc %VGPR(reg)
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# define TEST_ZERO(reg) test %VGPR(reg), %VGPR(reg)
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# define TO_32BIT_P1(reg) /* Do nothing. */
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# define TO_32BIT_P2(reg) /* Do nothing. */
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# define TO_32BIT(reg) /* Do nothing. */
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# define VEC_CMP VPCMPEQ
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# elif VEC_SIZE == 64
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# define TEST_ZERO_VCMP(reg) TEST_ZERO(reg)
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# define TEST_ZERO(reg) neg %VGPR(reg)
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/* VEC_SIZE == 64 needs to reduce the 64-bit mask to a 32-bit
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int. We have two methods for this. If the mask with branched
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on, we use `neg` for the branch then `sbb` to get the 32-bit
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return. If the mask was no branched on, we just use
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`popcntq`. */
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# define TO_32BIT_P1(reg) TEST_ZERO(reg)
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# define TO_32BIT_P2(reg) sbb %VGPR_SZ(reg, 32), %VGPR_SZ(reg, 32)
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# define TO_32BIT(reg) popcntq %reg, %reg
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# define VEC_CMP VPCMPNEQ
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# else
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# error "Unsupported VEC_SIZE"
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# endif
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# define VMOVU_MASK vmovdqu8
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# define VMOVU vmovdqu64
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# define VPCMP vpcmpub
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# define VPCMPNEQ vpcmpneqb
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# define VPCMPEQ vpcmpeqb
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# define VPTEST vptestmb
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# define VEC_SIZE 32
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# define PAGE_SIZE 4096
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# define YMM0 ymm16
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# define YMM1 ymm17
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# define YMM2 ymm18
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# define YMM3 ymm19
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# define YMM4 ymm20
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# define YMM5 ymm21
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# define YMM6 ymm22
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.section .text.evex, "ax", @progbits
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.section SECTION(.text), "ax", @progbits
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ENTRY_P2ALIGN (MEMCMPEQ, 6)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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@ -69,47 +98,54 @@ ENTRY_P2ALIGN (MEMCMPEQ, 6)
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ja L(more_1x_vec)
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/* Create mask of bytes that are guranteed to be valid because
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of length (edx). Using masked movs allows us to skip checks for
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page crosses/zero size. */
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movl $-1, %ecx
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bzhil %edx, %ecx, %ecx
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kmovd %ecx, %k2
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of length (edx). Using masked movs allows us to skip checks
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for page crosses/zero size. */
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mov $-1, %VRAX
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bzhi %VRDX, %VRAX, %VRAX
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/* NB: A `jz` might be useful here. Page-faults that are
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invalidated by predicate execution (the evex mask) can be
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very slow. The expectation is this is not the norm so and
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"most" code will not regularly call 'memcmp' with length = 0
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and memory that is not wired up. */
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KMOV %VRAX, %k2
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/* Use masked loads as VEC_SIZE could page cross where length
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(edx) would not. */
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VMOVU_MASK (%rsi), %YMM2{%k2}
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VPCMP $4,(%rdi), %YMM2, %k1{%k2}
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kmovd %k1, %eax
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VMOVU_MASK (%rsi), %VMM(2){%k2}{z}
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VPCMPNEQ (%rdi), %VMM(2), %k1{%k2}
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KMOV %k1, %VRAX
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TO_32BIT (VRAX)
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ret
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.p2align 4,, 3
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L(last_1x_vec):
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %YMM1
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VPCMP $4, -(VEC_SIZE * 1)(%rdi, %rdx), %YMM1, %k1
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kmovd %k1, %eax
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %VMM(1)
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VPCMPNEQ -(VEC_SIZE * 1)(%rdi, %rdx), %VMM(1), %k1
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KMOV %k1, %VRAX
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TO_32BIT_P1 (rax)
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L(return_neq0):
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TO_32BIT_P2 (rax)
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ret
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.p2align 4
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.p2align 4,, 12
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L(more_1x_vec):
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/* From VEC + 1 to 2 * VEC. */
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VMOVU (%rsi), %YMM1
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VMOVU (%rsi), %VMM(1)
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/* Use compare not equals to directly check for mismatch. */
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VPCMP $4,(%rdi), %YMM1, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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VPCMPNEQ (%rdi), %VMM(1), %k1
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KMOV %k1, %VRAX
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TEST_ZERO (rax)
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jnz L(return_neq0)
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cmpq $(VEC_SIZE * 2), %rdx
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jbe L(last_1x_vec)
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/* Check second VEC no matter what. */
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VMOVU VEC_SIZE(%rsi), %YMM2
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VPCMP $4, VEC_SIZE(%rdi), %YMM2, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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VMOVU VEC_SIZE(%rsi), %VMM(2)
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VPCMPNEQ VEC_SIZE(%rdi), %VMM(2), %k1
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KMOV %k1, %VRAX
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TEST_ZERO (rax)
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jnz L(return_neq0)
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/* Less than 4 * VEC. */
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@ -117,16 +153,16 @@ L(more_1x_vec):
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jbe L(last_2x_vec)
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/* Check third and fourth VEC no matter what. */
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VMOVU (VEC_SIZE * 2)(%rsi), %YMM3
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VPCMP $4,(VEC_SIZE * 2)(%rdi), %YMM3, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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VMOVU (VEC_SIZE * 2)(%rsi), %VMM(3)
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VEC_CMP (VEC_SIZE * 2)(%rdi), %VMM(3), %k1
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KMOV %k1, %VRAX
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TEST_ZERO_VCMP (rax)
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jnz L(return_neq0)
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VMOVU (VEC_SIZE * 3)(%rsi), %YMM4
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VPCMP $4,(VEC_SIZE * 3)(%rdi), %YMM4, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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VMOVU (VEC_SIZE * 3)(%rsi), %VMM(4)
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VEC_CMP (VEC_SIZE * 3)(%rdi), %VMM(4), %k1
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KMOV %k1, %VRAX
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TEST_ZERO_VCMP (rax)
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jnz L(return_neq0)
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/* Go to 4x VEC loop. */
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@ -136,8 +172,8 @@ L(more_1x_vec):
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/* Handle remainder of size = 4 * VEC + 1 to 8 * VEC without any
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branches. */
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VMOVU -(VEC_SIZE * 4)(%rsi, %rdx), %YMM1
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VMOVU -(VEC_SIZE * 3)(%rsi, %rdx), %YMM2
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %VMM(1)
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %VMM(2)
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addq %rdx, %rdi
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/* Wait to load from s1 until addressed adjust due to
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@ -145,26 +181,32 @@ L(more_1x_vec):
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/* vpxor will be all 0s if s1 and s2 are equal. Otherwise it
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will have some 1s. */
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vpxorq -(VEC_SIZE * 4)(%rdi), %YMM1, %YMM1
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/* Ternary logic to xor -(VEC_SIZE * 3)(%rdi) with YMM2 while
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oring with YMM1. Result is stored in YMM1. */
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vpternlogd $0xde, -(VEC_SIZE * 3)(%rdi), %YMM1, %YMM2
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vpxorq -(VEC_SIZE * 1)(%rdi), %VMM(1), %VMM(1)
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/* Ternary logic to xor -(VEC_SIZE * 3)(%rdi) with VEC(2) while
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oring with VEC(1). Result is stored in VEC(1). */
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vpternlogd $0xde, -(VEC_SIZE * 2)(%rdi), %VMM(1), %VMM(2)
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %YMM3
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vpxorq -(VEC_SIZE * 2)(%rdi), %YMM3, %YMM3
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/* Or together YMM1, YMM2, and YMM3 into YMM3. */
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VMOVU -(VEC_SIZE)(%rsi, %rdx), %YMM4
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vpxorq -(VEC_SIZE)(%rdi), %YMM4, %YMM4
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cmpl $(VEC_SIZE * 6), %edx
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jbe L(4x_last_2x_vec)
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/* Or together YMM2, YMM3, and YMM4 into YMM4. */
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vpternlogd $0xfe, %YMM2, %YMM3, %YMM4
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VMOVU -(VEC_SIZE * 3)(%rsi, %rdx), %VMM(3)
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vpxorq -(VEC_SIZE * 3)(%rdi), %VMM(3), %VMM(3)
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/* Or together VEC(1), VEC(2), and VEC(3) into VEC(3). */
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VMOVU -(VEC_SIZE * 4)(%rsi, %rdx), %VMM(4)
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vpxorq -(VEC_SIZE * 4)(%rdi), %VMM(4), %VMM(4)
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/* Compare YMM4 with 0. If any 1s s1 and s2 don't match. */
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VPTEST %YMM4, %YMM4, %k1
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kmovd %k1, %eax
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/* Or together VEC(4), VEC(3), and VEC(2) into VEC(2). */
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vpternlogd $0xfe, %VMM(4), %VMM(3), %VMM(2)
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/* Compare VEC(4) with 0. If any 1s s1 and s2 don't match. */
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L(4x_last_2x_vec):
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VPTEST %VMM(2), %VMM(2), %k1
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KMOV %k1, %VRAX
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TO_32BIT (VRAX)
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ret
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.p2align 4
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.p2align 4,, 10
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L(more_8x_vec):
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/* Set end of s1 in rdx. */
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leaq -(VEC_SIZE * 4)(%rdi, %rdx), %rdx
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@ -175,67 +217,80 @@ L(more_8x_vec):
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andq $-VEC_SIZE, %rdi
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/* Adjust because first 4x vec where check already. */
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subq $-(VEC_SIZE * 4), %rdi
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.p2align 4
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.p2align 5,, 12
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.p2align 4,, 8
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L(loop_4x_vec):
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VMOVU (%rsi, %rdi), %YMM1
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vpxorq (%rdi), %YMM1, %YMM1
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VMOVU (%rsi, %rdi), %VMM(1)
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vpxorq (%rdi), %VMM(1), %VMM(1)
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VMOVU VEC_SIZE(%rsi, %rdi), %YMM2
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vpternlogd $0xde,(VEC_SIZE)(%rdi), %YMM1, %YMM2
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VMOVU VEC_SIZE(%rsi, %rdi), %VMM(2)
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vpternlogd $0xde, (VEC_SIZE)(%rdi), %VMM(1), %VMM(2)
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VMOVU (VEC_SIZE * 2)(%rsi, %rdi), %YMM3
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vpxorq (VEC_SIZE * 2)(%rdi), %YMM3, %YMM3
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VMOVU (VEC_SIZE * 2)(%rsi, %rdi), %VMM(3)
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vpxorq (VEC_SIZE * 2)(%rdi), %VMM(3), %VMM(3)
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VMOVU (VEC_SIZE * 3)(%rsi, %rdi), %YMM4
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vpxorq (VEC_SIZE * 3)(%rdi), %YMM4, %YMM4
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VMOVU (VEC_SIZE * 3)(%rsi, %rdi), %VMM(4)
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vpxorq (VEC_SIZE * 3)(%rdi), %VMM(4), %VMM(4)
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vpternlogd $0xfe, %YMM2, %YMM3, %YMM4
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VPTEST %YMM4, %YMM4, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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vpternlogd $0xfe, %VMM(2), %VMM(3), %VMM(4)
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VPTEST %VMM(4), %VMM(4), %k1
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KMOV %k1, %VRAX
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TEST_ZERO (rax)
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jnz L(return_neq2)
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subq $-(VEC_SIZE * 4), %rdi
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cmpq %rdx, %rdi
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jb L(loop_4x_vec)
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subq %rdx, %rdi
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VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %YMM4
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vpxorq (VEC_SIZE * 3)(%rdx), %YMM4, %YMM4
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VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %VMM(4)
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vpxorq (VEC_SIZE * 3)(%rdx), %VMM(4), %VMM(4)
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/* rdi has 4 * VEC_SIZE - remaining length. */
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cmpl $(VEC_SIZE * 3), %edi
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jae L(8x_last_1x_vec)
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/* Load regardless of branch. */
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VMOVU (VEC_SIZE * 2)(%rsi, %rdx), %YMM3
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/* Ternary logic to xor (VEC_SIZE * 2)(%rdx) with YMM3 while
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oring with YMM4. Result is stored in YMM4. */
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vpternlogd $0xf6,(VEC_SIZE * 2)(%rdx), %YMM3, %YMM4
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VMOVU (VEC_SIZE * 2)(%rsi, %rdx), %VMM(3)
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/* Ternary logic to xor (VEC_SIZE * 2)(%rdx) with VEC(3) while
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oring with VEC(4). Result is stored in VEC(4). */
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vpternlogd $0xf6, (VEC_SIZE * 2)(%rdx), %VMM(3), %VMM(4)
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/* Seperate logic as we can only use testb for VEC_SIZE == 64.
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*/
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# if VEC_SIZE == 64
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testb %dil, %dil
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js L(8x_last_2x_vec)
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# else
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cmpl $(VEC_SIZE * 2), %edi
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jae L(8x_last_2x_vec)
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jge L(8x_last_2x_vec)
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# endif
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VMOVU VEC_SIZE(%rsi, %rdx), %YMM2
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vpxorq VEC_SIZE(%rdx), %YMM2, %YMM2
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VMOVU VEC_SIZE(%rsi, %rdx), %VMM(2)
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vpxorq VEC_SIZE(%rdx), %VMM(2), %VMM(2)
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VMOVU (%rsi, %rdx), %YMM1
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vpxorq (%rdx), %YMM1, %YMM1
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VMOVU (%rsi, %rdx), %VMM(1)
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vpxorq (%rdx), %VMM(1), %VMM(1)
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vpternlogd $0xfe, %YMM1, %YMM2, %YMM4
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vpternlogd $0xfe, %VMM(1), %VMM(2), %VMM(4)
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L(8x_last_1x_vec):
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L(8x_last_2x_vec):
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VPTEST %YMM4, %YMM4, %k1
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kmovd %k1, %eax
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VPTEST %VMM(4), %VMM(4), %k1
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KMOV %k1, %VRAX
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TO_32BIT_P1 (rax)
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L(return_neq2):
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TO_32BIT_P2 (rax)
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ret
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.p2align 4,, 8
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.p2align 4,, 4
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L(last_2x_vec):
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %YMM1
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vpxorq -(VEC_SIZE * 2)(%rdi, %rdx), %YMM1, %YMM1
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %YMM2
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vpternlogd $0xde, -(VEC_SIZE * 1)(%rdi, %rdx), %YMM1, %YMM2
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VPTEST %YMM2, %YMM2, %k1
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kmovd %k1, %eax
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %VMM(1)
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vpxorq -(VEC_SIZE * 2)(%rdi, %rdx), %VMM(1), %VMM(1)
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %VMM(2)
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vpternlogd $0xde, -(VEC_SIZE * 1)(%rdi, %rdx), %VMM(1), %VMM(2)
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VPTEST %VMM(2), %VMM(2), %k1
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KMOV %k1, %VRAX
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TO_32BIT (VRAX)
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ret
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/* 1 Bytes from next cache line. */
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/* evex256: 1 Bytes from next cache line. evex512: 15 Bytes from
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next cache line. */
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END (MEMCMPEQ)
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#endif
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