AuroraMiddleware/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2024-09-21 00:50:04 +00:00
Code Issues Packages Projects Releases Wiki Activity

Set SH fpcsr register which read again.

Browse Source
This commit is contained in:
Kaz Kojima 2012-04-05 11:57:03 +09:00
parent 8a53f50f2a
commit 2ecccfc97a
3 changed files with 14 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ChangeLog
View File

@ -1,3 +1,9 @@
2012-04-05 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sysdeps/sh/sh4/fpu/fegetenv.c (fegetenv): Set fpscr register which
read again.
* sysdeps/sh/sh4/fpu/ftestexcept.c: Likewise.
2012-04-05 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sysdeps/sh/sh4/fpu/fraiseexcpt.c (feraiseexcept): Produce

6
sysdeps/sh/sh4/fpu/fegetenv.c
View File

@ -1,5 +1,5 @@
/* Store current floating-point environment.
Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright (C) 1997, 1998, 1999, 2000, 2012 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
@ -24,6 +24,10 @@ fegetenv (fenv_t *envp)
{
unsigned long int temp;
_FPU_GETCW (temp);
/* When read fpscr, this was initialized.
We need to rewrite value of temp. */
_FPU_SETCW (temp);
envp->__fpscr = temp;
return 0;

3
sysdeps/sh/sh4/fpu/ftestexcept.c
View File

@ -26,6 +26,9 @@ fetestexcept (int excepts)
/* Get current exceptions. */
_FPU_GETCW (temp);
/* When read fpscr, this was initialized.
We need to rewrite value of temp. */
_FPU_SETCW (temp);
return temp & excepts & FE_ALL_EXCEPT;
}