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[PATCH] [AArch64] Optional trapping exceptions support.

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Trapping exceptions in AArch64 are optional.  The relevant exception
control bits in FPCR are are defined as RES0 hence the absence of
support can be detected by reading back the FPCR and comparing with
the desired value.
This commit is contained in:
Marcus Shawcroft 2014-03-07 14:05:20 +00:00
parent 6f99f280b0
commit 302949e294
3 changed files with 29 additions and 0 deletions
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6
ChangeLog
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@ -1,3 +1,9 @@
2014-03-07 Marcus Shawcroft <marcus.shawcroft@arm.com>
* sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept): Detect and
error absence of trapping exception support.
* sysdeps/aarch64/fpu/fesetenv.c (fesetenv): Likewise.
2014-03-07 Joseph Myers <joseph@codesourcery.com>
* catgets/Makefile (tests-special): Add $(objpfx)sample.SJIS.cat.

13
sysdeps/aarch64/fpu/feenablxcpt.c
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@ -35,5 +35,18 @@ feenableexcept (int excepts)
_FPU_SETCW (fpcr);
/* Trapping exceptions are optional in AArch64 the relevant enable
bits in FPCR are RES0 hence the absence of support can be
detected by reading back the FPCR and comparing with the required
value. */
if (excepts)
{
fpu_control_t updated_fpcr;
_FPU_GETCW (updated_fpcr);
if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
return -1;
}
return original_excepts;
}

10
sysdeps/aarch64/fpu/fesetenv.c
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@ -24,6 +24,7 @@ fesetenv (const fenv_t *envp)
{
fpu_control_t fpcr;
fpu_fpsr_t fpsr;
fpu_control_t updated_fpcr;
_FPU_GETCW (fpcr);
_FPU_GETFPSR (fpsr);
@ -51,6 +52,15 @@ fesetenv (const fenv_t *envp)
_FPU_SETCW (fpcr);
/* Trapping exceptions are optional in AArch64 the relevant enable
bits in FPCR are RES0 hence the absence of support can be
detected by reading back the FPCR and comparing with the required
value. */
_FPU_GETCW (updated_fpcr);
if ((updated_fpcr & fpcr) != fpcr)
return 1;
return 0;
}