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Improve fesetenv performance by avoiding unnecessary FPSR/FPCR reads/writes.
It uses the same logic as the ARM version. The common case removes 1 FPSR and 1 FPCR read. For FE_DFL_ENV and FE_NOMASK_ENV a FPCR read is avoided in case the FPCR does not change.
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@ -1,3 +1,8 @@
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2015-08-05 Wilco Dijkstra <wdijkstr@arm.com>
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* sysdeps/aarch64/fpu/fesetenv.c (fesetenv):
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Optimize to reduce FPCR/FPSR accesses.
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2015-08-05 H.J. Lu <hongjiu.lu@intel.com>
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* locale/loadarchive.c (_nl_archive_subfreeres): Also check
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@ -29,8 +29,20 @@ __fesetenv (const fenv_t *envp)
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fpu_fpsr_t fpsr_new;
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_FPU_GETCW (fpcr);
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_FPU_GETFPSR (fpsr);
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if ((envp != FE_DFL_ENV) && (envp != FE_NOMASK_ENV))
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{
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/* The new FPCR/FPSR are valid, so don't merge the reserved flags. */
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fpcr_new = envp->__fpcr;
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if (fpcr != fpcr_new)
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_FPU_SETCW (fpcr_new);
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_FPU_SETFPSR (envp->__fpsr);
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return 0;
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}
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_FPU_GETFPSR (fpsr);
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fpcr_new = fpcr & _FPU_RESERVED;
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fpsr_new = fpsr & _FPU_FPSR_RESERVED;
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@ -39,31 +51,25 @@ __fesetenv (const fenv_t *envp)
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fpcr_new |= _FPU_DEFAULT;
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fpsr_new |= _FPU_FPSR_DEFAULT;
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}
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else if (envp == FE_NOMASK_ENV)
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else
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{
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fpcr_new |= _FPU_FPCR_IEEE;
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fpsr_new |= _FPU_FPSR_IEEE;
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}
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else
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{
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fpcr_new |= envp->__fpcr & ~_FPU_RESERVED;
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fpsr_new |= envp->__fpsr & ~_FPU_FPSR_RESERVED;
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}
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if (fpsr != fpsr_new)
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_FPU_SETFPSR (fpsr_new);
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if (fpcr != fpcr_new)
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{
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_FPU_SETCW (fpcr_new);
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/* Trapping exceptions are optional in AArch64 the relevant enable
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bits in FPCR are RES0 hence the absence of support can be
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detected by reading back the FPCR and comparing with the required
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value. */
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/* Trapping exceptions are optional in AArch64; the relevant enable
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bits in FPCR are RES0 hence the absence of support can be detected
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by reading back the FPCR and comparing with the required value. */
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_FPU_GETCW (updated_fpcr);
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if ((updated_fpcr & fpcr_new) != fpcr_new)
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return 1;
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return fpcr_new & ~updated_fpcr;
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}
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return 0;
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}
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