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Use x86-64 cacheinfo.c and sysconf.c for x86
Since _dl_x86_cpu_features is always available, we can use x86-64 cacheinfo.c and sysconf.c for both i386 and x86-64. * sysdeps/i386/i686/Makefile [$(subdir) == string] (sysdep_routines): Moved to ... * sysdeps/i386/Makefile: Here. * sysdeps/i386/i686/cacheinfo.c: Moved to ... * sysdeps/i386/cacheinfo.c: Here. * sysdeps/unix/sysv/linux/i386/sysconf.c: Removed. * sysdeps/unix/sysv/linux/i386/i686/sysconf.c: Likewise. * sysdeps/unix/sysv/linux/x86_64/sysconf.c: Moved to ... * sysdeps/unix/sysv/linux/x86/sysconf.c: Here.
This commit is contained in:
H.J. Lu
parent
477fa2c843
commit
3552daa7ac
14
ChangeLog
14
ChangeLog
@ -1,4 +1,16 @@
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2015-08-10 H.J. Lu <hongjiu.lu@intel.com>
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2015-08-19 H.J. Lu <hongjiu.lu@intel.com>
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* sysdeps/i386/i686/Makefile
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[$(subdir) == string] (sysdep_routines): Moved to ...
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* sysdeps/i386/Makefile: Here.
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* sysdeps/i386/i686/cacheinfo.c: Moved to ...
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* sysdeps/i386/cacheinfo.c: Here.
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* sysdeps/unix/sysv/linux/i386/sysconf.c: Removed.
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* sysdeps/unix/sysv/linux/i386/i686/sysconf.c: Likewise.
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* sysdeps/unix/sysv/linux/x86_64/sysconf.c: Moved to ...
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* sysdeps/unix/sysv/linux/x86/sysconf.c: Here.
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2015-08-19 H.J. Lu <hongjiu.lu@intel.com>
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* sysdeps/x86/cpu-features.h (HAS_I586): Defined to 1 if
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__i586__ is defined.
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@ -5,6 +5,10 @@ asm-CPPFLAGS += -DGAS_SYNTAX
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# The i386 `long double' is a distinct type we support.
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long-double-fcts = yes
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ifeq ($(subdir),string)
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sysdep_routines += cacheinfo
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endif
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ifeq ($(subdir),gmon)
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sysdep_routines += i386-mcount
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endif
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@ -1,10 +1,6 @@
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# So that we can test __m128's alignment
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stack-align-test-flags += -msse
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ifeq ($(subdir),string)
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sysdep_routines += cacheinfo
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endif
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ifeq (yes,$(config-asflags-i686))
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CFLAGS-.o += -Wa,-mtune=i686
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CFLAGS-.os += -Wa,-mtune=i686
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@ -1 +0,0 @@
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#include <sysdeps/unix/sysv/linux/x86_64/sysconf.c>
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@ -1,509 +0,0 @@
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/* Get file-specific information about a file. Linux version.
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Copyright (C) 2003-2015 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <assert.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <hp-timing.h>
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static long int linux_sysconf (int name);
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static long int __attribute__ ((noinline))
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handle_i486 (int name)
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{
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/* The processor only has a unified level 1 cache of 8k. */
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switch (name)
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{
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case _SC_LEVEL1_ICACHE_SIZE:
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case _SC_LEVEL1_DCACHE_SIZE:
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return 8 * 1024;
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case _SC_LEVEL1_ICACHE_ASSOC:
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case _SC_LEVEL1_DCACHE_ASSOC:
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// XXX Anybody know this?
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return 0;
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case _SC_LEVEL1_ICACHE_LINESIZE:
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case _SC_LEVEL1_DCACHE_LINESIZE:
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// XXX Anybody know for sure?
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return 16;
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case _SC_LEVEL2_CACHE_SIZE:
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case _SC_LEVEL2_CACHE_ASSOC:
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case _SC_LEVEL2_CACHE_LINESIZE:
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case _SC_LEVEL3_CACHE_SIZE:
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case _SC_LEVEL3_CACHE_ASSOC:
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case _SC_LEVEL3_CACHE_LINESIZE:
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case _SC_LEVEL4_CACHE_SIZE:
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case _SC_LEVEL4_CACHE_ASSOC:
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/* Not available. */
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break;
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default:
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assert (! "cannot happen");
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}
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return -1;
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}
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static const struct intel_02_cache_info
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{
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unsigned char idx;
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unsigned char assoc;
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unsigned char linesize;
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unsigned char rel_name;
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unsigned int size;
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} intel_02_known [] =
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{
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#define M(sc) ((sc) - _SC_LEVEL1_ICACHE_SIZE)
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{ 0x06, 4, 32, M(_SC_LEVEL1_ICACHE_SIZE), 8192 },
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{ 0x08, 4, 32, M(_SC_LEVEL1_ICACHE_SIZE), 16384 },
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{ 0x09, 4, 32, M(_SC_LEVEL1_ICACHE_SIZE), 32768 },
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{ 0x0a, 2, 32, M(_SC_LEVEL1_DCACHE_SIZE), 8192 },
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{ 0x0c, 4, 32, M(_SC_LEVEL1_DCACHE_SIZE), 16384 },
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{ 0x0d, 4, 64, M(_SC_LEVEL1_DCACHE_SIZE), 16384 },
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{ 0x21, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
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{ 0x22, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 524288 },
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{ 0x23, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 1048576 },
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{ 0x25, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
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{ 0x29, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
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{ 0x2c, 8, 64, M(_SC_LEVEL1_DCACHE_SIZE), 32768 },
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{ 0x30, 8, 64, M(_SC_LEVEL1_ICACHE_SIZE), 32768 },
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{ 0x39, 4, 64, M(_SC_LEVEL2_CACHE_SIZE), 131072 },
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{ 0x3a, 6, 64, M(_SC_LEVEL2_CACHE_SIZE), 196608 },
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{ 0x3b, 2, 64, M(_SC_LEVEL2_CACHE_SIZE), 131072 },
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{ 0x3c, 4, 64, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
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{ 0x3d, 6, 64, M(_SC_LEVEL2_CACHE_SIZE), 393216 },
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{ 0x3e, 4, 64, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
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{ 0x3f, 2, 64, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
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{ 0x41, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 131072 },
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{ 0x42, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
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{ 0x43, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
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{ 0x44, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
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{ 0x45, 4, 32, M(_SC_LEVEL2_CACHE_SIZE), 2097152 },
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{ 0x46, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
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{ 0x47, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
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{ 0x48, 12, 64, M(_SC_LEVEL2_CACHE_SIZE), 3145728 },
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{ 0x49, 16, 64, M(_SC_LEVEL2_CACHE_SIZE), 4194304 },
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{ 0x4a, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 6291456 },
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{ 0x4b, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
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{ 0x4c, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
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{ 0x4d, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 16777216 },
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{ 0x4e, 24, 64, M(_SC_LEVEL2_CACHE_SIZE), 6291456 },
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{ 0x60, 8, 64, M(_SC_LEVEL1_DCACHE_SIZE), 16384 },
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{ 0x66, 4, 64, M(_SC_LEVEL1_DCACHE_SIZE), 8192 },
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{ 0x67, 4, 64, M(_SC_LEVEL1_DCACHE_SIZE), 16384 },
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{ 0x68, 4, 64, M(_SC_LEVEL1_DCACHE_SIZE), 32768 },
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{ 0x78, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
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{ 0x79, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 131072 },
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{ 0x7a, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
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{ 0x7b, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
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{ 0x7c, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
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{ 0x7d, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 2097152 },
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{ 0x7f, 2, 64, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
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{ 0x82, 8, 32, M(_SC_LEVEL2_CACHE_SIZE), 262144 },
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{ 0x83, 8, 32, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
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{ 0x84, 8, 32, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
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{ 0x85, 8, 32, M(_SC_LEVEL2_CACHE_SIZE), 2097152 },
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{ 0x86, 4, 64, M(_SC_LEVEL2_CACHE_SIZE), 524288 },
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{ 0x87, 8, 64, M(_SC_LEVEL2_CACHE_SIZE), 1048576 },
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{ 0xd0, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 524288 },
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{ 0xd1, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 1048576 },
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{ 0xd2, 4, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
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{ 0xd6, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 1048576 },
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{ 0xd7, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
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{ 0xd8, 8, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
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{ 0xdc, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
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{ 0xdd, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
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{ 0xde, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
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{ 0xe2, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
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{ 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
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{ 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
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{ 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
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{ 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 },
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{ 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 },
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};
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#define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
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static int
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intel_02_known_compare (const void *p1, const void *p2)
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{
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const struct intel_02_cache_info *i1;
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const struct intel_02_cache_info *i2;
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i1 = (const struct intel_02_cache_info *) p1;
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i2 = (const struct intel_02_cache_info *) p2;
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if (i1->idx == i2->idx)
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return 0;
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return i1->idx < i2->idx ? -1 : 1;
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}
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static long int
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__attribute__ ((noinline))
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intel_check_word (int name, unsigned int value, bool *has_level_2,
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bool *no_level_2_or_3)
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{
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if ((value & 0x80000000) != 0)
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/* The register value is reserved. */
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return 0;
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/* Fold the name. The _SC_ constants are always in the order SIZE,
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ASSOC, LINESIZE. */
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int folded_rel_name = (M(name) / 3) * 3;
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while (value != 0)
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{
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unsigned int byte = value & 0xff;
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if (byte == 0x40)
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{
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*no_level_2_or_3 = true;
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if (folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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/* No need to look further. */
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break;
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}
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else if (byte == 0xff)
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{
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/* CPUID leaf 0x4 contains all the information. We need to
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iterate over it. */
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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unsigned int round = 0;
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while (1)
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{
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asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (4), "2" (round));
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enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
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if (type == null)
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/* That was the end. */
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break;
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unsigned int level = (eax >> 5) & 0x7;
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if ((level == 1 && type == data
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&& folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
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|| (level == 1 && type == inst
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&& folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
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|| (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
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|| (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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|| (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE)))
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{
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unsigned int offset = M(name) - folded_rel_name;
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if (offset == 0)
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/* Cache size. */
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return (((ebx >> 22) + 1)
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* (((ebx >> 12) & 0x3ff) + 1)
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* ((ebx & 0xfff) + 1)
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* (ecx + 1));
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if (offset == 1)
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return (ebx >> 22) + 1;
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assert (offset == 2);
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return (ebx & 0xfff) + 1;
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}
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|
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++round;
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}
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/* There is no other cache information anywhere else. */
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break;
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}
|
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else
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{
|
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if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
|
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{
|
||||
/* Intel reused this value. For family 15, model 6 it
|
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specifies the 3rd level cache. Otherwise the 2nd
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level cache. */
|
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
|
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unsigned int edx;
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asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
|
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: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
|
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: "0" (1));
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|
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unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
|
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unsigned int model = ((((eax >>16) & 0xf) << 4)
|
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+ ((eax >> 4) & 0xf));
|
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if (family == 15 && model == 6)
|
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{
|
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/* The level 3 cache is encoded for this model like
|
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the level 2 cache is for other models. Pretend
|
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the caller asked for the level 2 cache. */
|
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name = (_SC_LEVEL2_CACHE_SIZE
|
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+ (name - _SC_LEVEL3_CACHE_SIZE));
|
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folded_rel_name = M(_SC_LEVEL2_CACHE_SIZE);
|
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}
|
||||
}
|
||||
|
||||
struct intel_02_cache_info *found;
|
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struct intel_02_cache_info search;
|
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|
||||
search.idx = byte;
|
||||
found = bsearch (&search, intel_02_known, nintel_02_known,
|
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sizeof (intel_02_known[0]), intel_02_known_compare);
|
||||
if (found != NULL)
|
||||
{
|
||||
if (found->rel_name == folded_rel_name)
|
||||
{
|
||||
unsigned int offset = M(name) - folded_rel_name;
|
||||
|
||||
if (offset == 0)
|
||||
/* Cache size. */
|
||||
return found->size;
|
||||
if (offset == 1)
|
||||
return found->assoc;
|
||||
|
||||
assert (offset == 2);
|
||||
return found->linesize;
|
||||
}
|
||||
|
||||
if (found->rel_name == M(_SC_LEVEL2_CACHE_SIZE))
|
||||
*has_level_2 = true;
|
||||
}
|
||||
}
|
||||
|
||||
/* Next byte for the next round. */
|
||||
value >>= 8;
|
||||
}
|
||||
|
||||
/* Nothing found. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static long int __attribute__ ((noinline))
|
||||
handle_intel (int name, unsigned int maxidx)
|
||||
{
|
||||
if (maxidx < 2)
|
||||
{
|
||||
// XXX Do such processors exist? When we know we can fill in some
|
||||
// values.
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* OK, we can use the CPUID instruction to get all info about the
|
||||
caches. */
|
||||
unsigned int cnt = 0;
|
||||
unsigned int max = 1;
|
||||
long int result = 0;
|
||||
bool no_level_2_or_3 = false;
|
||||
bool has_level_2 = false;
|
||||
while (cnt++ < max)
|
||||
{
|
||||
unsigned int eax;
|
||||
unsigned int ebx;
|
||||
unsigned int ecx;
|
||||
unsigned int edx;
|
||||
asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
|
||||
: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
|
||||
: "0" (2));
|
||||
|
||||
/* The low byte of EAX in the first round contain the number of
|
||||
rounds we have to make. At least one, the one we are already
|
||||
doing. */
|
||||
if (cnt == 1)
|
||||
{
|
||||
max = eax & 0xff;
|
||||
eax &= 0xffffff00;
|
||||
}
|
||||
|
||||
/* Process the individual registers' value. */
|
||||
result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
|
||||
if (result != 0)
|
||||
return result;
|
||||
|
||||
result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
|
||||
if (result != 0)
|
||||
return result;
|
||||
}
|
||||
|
||||
if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
|
||||
&& no_level_2_or_3)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static long int __attribute__ ((noinline))
|
||||
handle_amd (int name)
|
||||
{
|
||||
unsigned int eax;
|
||||
unsigned int ebx;
|
||||
unsigned int ecx;
|
||||
unsigned int edx;
|
||||
asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
|
||||
: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
|
||||
: "0" (0x80000000));
|
||||
|
||||
if (name >= _SC_LEVEL3_CACHE_SIZE)
|
||||
return 0;
|
||||
|
||||
unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
|
||||
if (eax < fn)
|
||||
return 0;
|
||||
|
||||
asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
|
||||
: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
|
||||
: "0" (fn));
|
||||
|
||||
if (name < _SC_LEVEL1_DCACHE_SIZE)
|
||||
{
|
||||
name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
|
||||
ecx = edx;
|
||||
}
|
||||
|
||||
switch (name)
|
||||
{
|
||||
case _SC_LEVEL1_DCACHE_SIZE:
|
||||
return (ecx >> 14) & 0x3fc00;
|
||||
case _SC_LEVEL1_DCACHE_ASSOC:
|
||||
ecx >>= 16;
|
||||
if ((ecx & 0xff) == 0xff)
|
||||
/* Fully associative. */
|
||||
return (ecx << 2) & 0x3fc00;
|
||||
return ecx & 0xff;
|
||||
case _SC_LEVEL1_DCACHE_LINESIZE:
|
||||
return ecx & 0xff;
|
||||
case _SC_LEVEL2_CACHE_SIZE:
|
||||
return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
|
||||
case _SC_LEVEL2_CACHE_ASSOC:
|
||||
ecx >>= 12;
|
||||
switch (ecx & 0xf)
|
||||
{
|
||||
case 0:
|
||||
case 1:
|
||||
case 2:
|
||||
case 4:
|
||||
return ecx & 0xf;
|
||||
case 6:
|
||||
return 8;
|
||||
case 8:
|
||||
return 16;
|
||||
case 0xf:
|
||||
return (ecx << 6) & 0x3fffc00;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
case _SC_LEVEL2_CACHE_LINESIZE:
|
||||
return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
|
||||
default:
|
||||
assert (! "cannot happen");
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
i386_i486_test (void)
|
||||
{
|
||||
int eflags;
|
||||
int ac;
|
||||
asm volatile ("pushfl;\n\t"
|
||||
"popl %0;\n\t"
|
||||
"movl $0x240000, %1;\n\t"
|
||||
"xorl %0, %1;\n\t"
|
||||
"pushl %1;\n\t"
|
||||
"popfl;\n\t"
|
||||
"pushfl;\n\t"
|
||||
"popl %1;\n\t"
|
||||
"xorl %0, %1;\n\t"
|
||||
"pushl %0;\n\t"
|
||||
"popfl"
|
||||
: "=r" (eflags), "=r" (ac));
|
||||
|
||||
return ac;
|
||||
}
|
||||
|
||||
|
||||
/* Get the value of the system variable NAME. */
|
||||
long int
|
||||
__sysconf (int name)
|
||||
{
|
||||
/* All the remainder, except the cache information, is handled in
|
||||
the generic code. */
|
||||
if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
|
||||
return linux_sysconf (name);
|
||||
|
||||
/* Recognize i386 and compatible. These don't have any cache on
|
||||
board. */
|
||||
int ac = i386_i486_test ();
|
||||
|
||||
if (ac == 0)
|
||||
/* This is an i386. */
|
||||
// XXX Is this true for all brands?
|
||||
return -1;
|
||||
|
||||
/* Detect i486, the last Intel processor without CPUID. */
|
||||
if ((ac & (1 << 21)) == 0)
|
||||
{
|
||||
/* No CPUID. */
|
||||
// XXX Fill in info about other brands. For now only Intel.
|
||||
return handle_i486 (name);
|
||||
}
|
||||
|
||||
/* Find out what brand of processor. */
|
||||
unsigned int eax;
|
||||
unsigned int ebx;
|
||||
unsigned int ecx;
|
||||
unsigned int edx;
|
||||
asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
|
||||
: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
|
||||
: "0" (0));
|
||||
|
||||
/* This spells out "GenuineIntel". */
|
||||
if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
|
||||
return handle_intel (name, eax);
|
||||
|
||||
/* This spells out "AuthenticAMD". */
|
||||
if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
|
||||
return handle_amd (name);
|
||||
|
||||
// XXX Fill in more vendors.
|
||||
|
||||
/* CPU not known, we have no information. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Now the generic Linux version. */
|
||||
#undef __sysconf
|
||||
#define __sysconf static linux_sysconf
|
||||
#include "../sysconf.c"
|
||||
Loading…
Reference in New Issue
Block a user