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Add support for some more motherboards.
This commit is contained in:
Ulrich Drepper
parent
7d4b96d50f
commit
38deee8be7
@ -1,4 +1,4 @@
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/* Copyright (C) 1992, 1996, 1997, 1998 Free Software Foundation, Inc.
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/* Copyright (C) 1992, 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by David Mosberger.
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@ -86,11 +86,21 @@
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#define TSUNAMI_IO_BASE (0x00000801fc000000UL + 0xfffffc0000000000UL)
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#define TSUNAMI_DENSE_MEM (0x0000080000000000UL + 0xfffffc0000000000UL)
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/* Polaris has SPARSE space, but we prefer to use only DENSE */
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/* because of some idiosyncracies in actually using SPARSE */
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#define POLARIS_IO_BASE (0xfffffcf9fc000000UL)
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#define POLARIS_DENSE_MEM (0xfffffcf900000000UL)
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typedef enum {
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IOSYS_UNKNOWN, IOSYS_JENSEN, IOSYS_APECS, IOSYS_CIA, IOSYS_T2,
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IOSYS_TSUNAMI, IOSYS_MCPCIA, IOSYS_GAMMA, IOSYS_CPUDEP
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IOSYS_TSUNAMI, IOSYS_MCPCIA, IOSYS_GAMMA, IOSYS_POLARIS,
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IOSYS_CPUDEP, IOSYS_PCIDEP
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} iosys_t;
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typedef enum {
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IOSWIZZLE_JENSEN, IOSWIZZLE_SPARSE, IOSWIZZLE_DENSE
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} ioswizzle_t;
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static struct io_system {
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int hae_shift;
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unsigned long int bus_memory_base;
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@ -105,7 +115,9 @@ static struct io_system {
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/* TSUNAMI */ {0, TSUNAMI_DENSE_MEM, 0, TSUNAMI_IO_BASE},
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/* MCPCIA */ {5, MCPCIA_DENSE_MEM, MCPCIA_SPARSE_MEM, MCPCIA_IO_BASE},
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/* GAMMA */ {5, GAMMA_DENSE_MEM, GAMMA_SPARSE_MEM, GAMMA_IO_BASE},
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/* CPUDEP */ {0, 0, 0, 0},
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/* POLARIS */ {0, POLARIS_DENSE_MEM, 0, POLARIS_IO_BASE},
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/* CPUDEP */ {0, 0, 0, 0}, /* for platforms dependent on CPU type */
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/* PCIDEP */ {0, 0, 0, 0}, /* for platforms dependent on core logic */
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};
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static struct platform {
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@ -116,7 +128,7 @@ static struct platform {
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{"Avanti", IOSYS_APECS},
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{"XL", IOSYS_APECS},
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{"Cabriolet", IOSYS_APECS},
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{"EB164", IOSYS_CIA},
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{"EB164", IOSYS_PCIDEP},
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{"EB64+", IOSYS_APECS},
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{"EB66", IOSYS_APECS},
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{"EB66P", IOSYS_APECS},
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@ -153,38 +165,27 @@ static struct {
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unsigned long int sparse_bus_memory_base;
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unsigned long int io_base;
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iosys_t sys;
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ioswizzle_t swiz;
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int hae_shift;
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} io;
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extern void __sethae (unsigned long int); /* we can't use asm/io.h */
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static inline unsigned long int
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port_to_cpu_addr (unsigned long int port, iosys_t iosys, int size)
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port_to_cpu_addr (unsigned long int port, ioswizzle_t ioswiz, int size)
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{
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if (iosys == IOSYS_JENSEN)
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return (port << 7) + ((size - 1) << 5) + io.base;
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else if (iosys == IOSYS_TSUNAMI)
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if (ioswiz == IOSWIZZLE_SPARSE)
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return (port << 5) + ((size - 1) << 3) + io.base;
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else if (ioswiz == IOSWIZZLE_DENSE)
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return port + io.base;
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else
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return (port << 5) + ((size - 1) << 3) + io.base;
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return (port << 7) + ((size - 1) << 5) + io.base;
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}
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static inline void
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inline_sethae (unsigned long int addr, iosys_t iosys)
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inline_sethae (unsigned long int addr, ioswizzle_t ioswiz)
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{
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if (iosys == IOSYS_JENSEN)
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{
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/* hae on the Jensen is bits 31:25 shifted right */
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addr >>= 25;
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if (addr != io.hae.cache)
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{
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__sethae (addr);
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io.hae.cache = addr;
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}
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}
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else
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if (ioswiz == IOSWIZZLE_SPARSE)
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{
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unsigned long int msb;
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@ -196,16 +197,25 @@ inline_sethae (unsigned long int addr, iosys_t iosys)
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io.hae.cache = msb;
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}
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}
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else
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{
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/* hae on the Jensen is bits 31:25 shifted right */
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addr >>= 25;
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if (addr != io.hae.cache)
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{
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__sethae (addr);
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io.hae.cache = addr;
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}
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}
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}
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static inline void
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inline_outb (unsigned char b, unsigned long int port, iosys_t iosys)
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inline_outb (unsigned char b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned int w;
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unsigned long int addr = port_to_cpu_addr (port, iosys, 1);
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 1);
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inline_sethae (0, iosys);
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inline_sethae (0, ioswiz);
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asm ("insbl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
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*(vuip)addr = w;
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mb ();
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@ -213,12 +223,12 @@ inline_outb (unsigned char b, unsigned long int port, iosys_t iosys)
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static inline void
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inline_outw (unsigned short int b, unsigned long int port, iosys_t iosys)
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inline_outw (unsigned short int b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned int w;
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unsigned long int addr = port_to_cpu_addr (port, iosys, 2);
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 2);
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inline_sethae (0, iosys);
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inline_sethae (0, ioswiz);
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asm ("inswl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
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*(vuip)addr = w;
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mb ();
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@ -226,22 +236,22 @@ inline_outw (unsigned short int b, unsigned long int port, iosys_t iosys)
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static inline void
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inline_outl (unsigned int b, unsigned long int port, iosys_t iosys)
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inline_outl (unsigned int b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
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inline_sethae (0, iosys);
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inline_sethae (0, ioswiz);
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*(vuip)addr = b;
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mb ();
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}
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static inline unsigned int
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inline_inb (unsigned long int port, iosys_t iosys)
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inline_inb (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int result, addr = port_to_cpu_addr (port, iosys, 1);
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unsigned long int result, addr = port_to_cpu_addr (port, ioswiz, 1);
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inline_sethae (0, iosys);
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inline_sethae (0, ioswiz);
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result = *(vuip) addr;
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result >>= (port & 3) * 8;
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return 0xffUL & result;
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@ -249,11 +259,11 @@ inline_inb (unsigned long int port, iosys_t iosys)
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static inline unsigned int
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inline_inw (unsigned long int port, iosys_t iosys)
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inline_inw (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int result, addr = port_to_cpu_addr (port, iosys, 2);
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unsigned long int result, addr = port_to_cpu_addr (port, ioswiz, 2);
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inline_sethae (0, iosys);
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inline_sethae (0, ioswiz);
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result = *(vuip) addr;
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result >>= (port & 3) * 8;
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return 0xffffUL & result;
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@ -261,11 +271,11 @@ inline_inw (unsigned long int port, iosys_t iosys)
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static inline unsigned int
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inline_inl (unsigned long int port, iosys_t iosys)
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inline_inl (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
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inline_sethae (0, iosys);
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inline_sethae (0, ioswiz);
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return *(vuip) addr;
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}
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@ -274,115 +284,115 @@ inline_inl (unsigned long int port, iosys_t iosys)
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* and whose core logic supports I/O space accesses utilizing them.
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*
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* These routines could be used by MIATA, for example, because it has
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* and EV56 plus PYXIS, but it currently uses SPARSE anyway.
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* and EV56 plus PYXIS, but it currently uses SPARSE anyway. This is
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* also true of RX164 which used POLARIS, but we will choose to use
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* these routines in that case instead of SPARSE.
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*
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* These routines are necessary for TSUNAMI/TYPHOON based platforms,
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* which will have (at least) EV6.
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*/
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static inline void
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inline_bwx_outb (unsigned char b, unsigned long int port, iosys_t iosys)
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static inline unsigned long int
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dense_port_to_cpu_addr (unsigned long int port)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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return port + io.base;
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}
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static inline void
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inline_bwx_outb (unsigned char b, unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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__asm__ __volatile__ ("stb %1,%0" : : "m"(*(unsigned char *)addr), "r"(b));
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mb ();
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}
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static inline void
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inline_bwx_outw (unsigned short int b, unsigned long int port, iosys_t iosys)
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inline_bwx_outw (unsigned short int b, unsigned long int port)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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unsigned long int addr = dense_port_to_cpu_addr (port);
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__asm__ __volatile__ ("stw %1,%0" : : "m"(*(unsigned short *)addr), "r"(b));
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mb ();
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}
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static inline void
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inline_bwx_outl (unsigned int b, unsigned long int port, iosys_t iosys)
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inline_bwx_outl (unsigned int b, unsigned long int port)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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unsigned long int addr = dense_port_to_cpu_addr (port);
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*(vuip)addr = b;
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mb ();
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}
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static inline unsigned int
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inline_bwx_inb (unsigned long int port, iosys_t iosys)
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inline_bwx_inb (unsigned long int port)
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{
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unsigned long int r, addr = port_to_cpu_addr (port, iosys, 1);
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unsigned long int r, addr = dense_port_to_cpu_addr (port);
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__asm__ __volatile__ ("ldbu %0,%1" : "=r"(r) : "m"(*(unsigned char *)addr));
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return 0xffUL & r;
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}
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static inline unsigned int
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inline_bwx_inw (unsigned long int port, iosys_t iosys)
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inline_bwx_inw (unsigned long int port)
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{
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unsigned long int r, addr = port_to_cpu_addr (port, iosys, 1);
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unsigned long int r, addr = dense_port_to_cpu_addr (port);
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__asm__ __volatile__ ("ldwu %0,%1" : "=r"(r) : "m"(*(unsigned short *)addr));
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return 0xffffUL & r;
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}
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static inline unsigned int
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inline_bwx_inl (unsigned long int port, iosys_t iosys)
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inline_bwx_inl (unsigned long int port)
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{
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unsigned long int addr = port_to_cpu_addr (port, iosys, 4);
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unsigned long int addr = dense_port_to_cpu_addr (port);
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return *(vuip) addr;
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}
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/* macros to define routines with appropriate names and functions */
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#define DCL_SETHAE(name, iosys) \
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static void \
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name##_sethae (unsigned long int addr) \
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{ \
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inline_sethae (addr, IOSYS_##iosys); \
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/* these do either SPARSE or JENSEN swizzle */
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#define DCL_SETHAE(name, ioswiz) \
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static void \
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name##_sethae (unsigned long int addr) \
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{ \
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inline_sethae (addr, IOSWIZZLE_##ioswiz); \
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}
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#define DCL_OUT(name, func, type, iosys) \
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#define DCL_OUT(name, func, type, ioswiz) \
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static void \
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name##_##func (unsigned type b, unsigned long int addr) \
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{ \
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inline_##func (b, addr, IOSYS_##iosys); \
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inline_##func (b, addr, IOSWIZZLE_##ioswiz); \
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}
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#define DCL_IN(name, func, iosys) \
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#define DCL_IN(name, func, ioswiz) \
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static unsigned int \
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name##_##func (unsigned long int addr) \
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{ \
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return inline_##func (addr, IOSYS_##iosys); \
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return inline_##func (addr, IOSWIZZLE_##ioswiz); \
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}
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#define DCL_SETHAE_IGNORE(name, iosys) \
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static void \
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name##_sethae (unsigned long int addr) \
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{ \
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/* do nothing */ \
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}
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/* these do DENSE, so no swizzle is needed */
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#define DCL_OUT_BWX(name, func, type, iosys) \
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#define DCL_OUT_BWX(name, func, type) \
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static void \
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name##_##func (unsigned type b, unsigned long int addr) \
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{ \
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inline_bwx_##func (b, addr, IOSYS_##iosys); \
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inline_bwx_##func (b, addr); \
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}
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#define DCL_IN_BWX(name, func, iosys) \
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#define DCL_IN_BWX(name, func) \
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static unsigned int \
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name##_##func (unsigned long int addr) \
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{ \
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return inline_bwx_##func (addr, IOSYS_##iosys); \
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return inline_bwx_##func (addr); \
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}
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/* now declare/define the necessary routines */
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DCL_SETHAE(jensen, JENSEN)
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DCL_OUT(jensen, outb, char, JENSEN)
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@ -392,25 +402,22 @@ DCL_IN(jensen, inb, JENSEN)
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DCL_IN(jensen, inw, JENSEN)
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DCL_IN(jensen, inl, JENSEN)
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/* The APECS functions are also used for CIA since they are
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identical. */
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DCL_SETHAE(sparse, SPARSE)
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DCL_OUT(sparse, outb, char, SPARSE)
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DCL_OUT(sparse, outw, short int, SPARSE)
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DCL_OUT(sparse, outl, int, SPARSE)
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DCL_IN(sparse, inb, SPARSE)
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DCL_IN(sparse, inw, SPARSE)
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DCL_IN(sparse, inl, SPARSE)
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DCL_SETHAE(apecs, APECS)
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DCL_OUT(apecs, outb, char, APECS)
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DCL_OUT(apecs, outw, short int, APECS)
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DCL_OUT(apecs, outl, int, APECS)
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DCL_IN(apecs, inb, APECS)
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DCL_IN(apecs, inw, APECS)
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DCL_IN(apecs, inl, APECS)
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DCL_SETHAE_IGNORE(tsunami, TSUNAMI)
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DCL_OUT_BWX(tsunami, outb, char, TSUNAMI)
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DCL_OUT_BWX(tsunami, outw, short int, TSUNAMI)
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DCL_OUT_BWX(tsunami, outl, int, TSUNAMI)
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DCL_IN_BWX(tsunami, inb, TSUNAMI)
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DCL_IN_BWX(tsunami, inw, TSUNAMI)
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DCL_IN_BWX(tsunami, inl, TSUNAMI)
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DCL_OUT_BWX(dense, outb, char)
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DCL_OUT_BWX(dense, outw, short int)
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DCL_OUT_BWX(dense, outl, int)
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DCL_IN_BWX(dense, inb)
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DCL_IN_BWX(dense, inw)
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DCL_IN_BWX(dense, inl)
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/* define the "swizzle" switch */
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static struct ioswtch ioswtch[] = {
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{
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jensen_sethae,
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@ -418,18 +425,63 @@ static struct ioswtch ioswtch[] = {
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jensen_inb, jensen_inw, jensen_inl
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},
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{
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apecs_sethae,
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apecs_outb, apecs_outw, apecs_outl,
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apecs_inb, apecs_inw, apecs_inl
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sparse_sethae,
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sparse_outb, sparse_outw, sparse_outl,
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sparse_inb, sparse_inw, sparse_inl
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},
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{
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tsunami_sethae,
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tsunami_outb, tsunami_outw, tsunami_outl,
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tsunami_inb, tsunami_inw, tsunami_inl
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NULL,
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dense_outb, dense_outw, dense_outl,
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dense_inb, dense_inw, dense_inl
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}
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};
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|
||||
/* routine to process the /proc/cpuinfo information into the fields */
|
||||
/* that are required for correctly determining the platform parameters */
|
||||
|
||||
char systype[256]; /* system type field */
|
||||
char sysvari[256]; /* system variation field */
|
||||
char cpumodel[256]; /* cpu model field */
|
||||
int got_type, got_vari, got_model;
|
||||
|
||||
static int
|
||||
process_cpuinfo(void)
|
||||
{
|
||||
char dummy[256];
|
||||
FILE * fp;
|
||||
|
||||
fp = fopen (PATH_CPUINFO, "r");
|
||||
if (!fp)
|
||||
return 0;
|
||||
|
||||
got_type = got_vari = got_model = 0;
|
||||
systype[0] = sysvari[0] = cpumodel[0] = 0;
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (fgets (dummy, 256, fp) == NULL) break;
|
||||
/* fprintf(stderr, "read: %s", dummy); */
|
||||
if (!got_type &&
|
||||
sscanf (dummy, "system type : %256[^\n]\n", systype) == 1)
|
||||
got_type = 1;
|
||||
if (!got_vari &&
|
||||
sscanf (dummy, "system variation : %256[^\n]\n", sysvari) == 1)
|
||||
got_vari = 1;
|
||||
if (!got_model &&
|
||||
sscanf (dummy, "cpu model : %256[^\n]\n", cpumodel) == 1)
|
||||
got_model = 1;
|
||||
}
|
||||
|
||||
fclose (fp);
|
||||
|
||||
#if 1
|
||||
fprintf(stderr, "system type: %s\n", systype);
|
||||
fprintf(stderr, "system vari: %s\n", sysvari);
|
||||
fprintf(stderr, "cpu model: %s\n", cpumodel);
|
||||
#endif
|
||||
|
||||
return got_type+got_vari+got_model;
|
||||
}
|
||||
/*
|
||||
* Initialize I/O system. To determine what I/O system we're dealing
|
||||
* with, we first try to read the value of symlink PATH_ALPHA_SYSTYPE,
|
||||
@ -443,7 +495,6 @@ static struct ioswtch ioswtch[] = {
|
||||
static int
|
||||
init_iosys (void)
|
||||
{
|
||||
char systype[256];
|
||||
int i, n;
|
||||
|
||||
n = readlink (PATH_ALPHA_SYSTYPE, systype, sizeof (systype) - 1);
|
||||
@ -456,7 +507,8 @@ init_iosys (void)
|
||||
&io.bus_memory_base, &io.sparse_bus_memory_base) == 4)
|
||||
{
|
||||
io.sys = IOSYS_UNKNOWN;
|
||||
io.swp = &ioswtch[1];
|
||||
io.swiz = IOSWIZZLE_SPARSE;
|
||||
io.swp = &ioswtch[IOSWIZZLE_SPARSE];
|
||||
return 0;
|
||||
}
|
||||
/* else we're likely going to fail with the system match below */
|
||||
@ -464,22 +516,9 @@ init_iosys (void)
|
||||
}
|
||||
else
|
||||
{
|
||||
FILE * fp;
|
||||
n = process_cpuinfo();
|
||||
|
||||
fp = fopen (PATH_CPUINFO, "r");
|
||||
if (!fp)
|
||||
return -1;
|
||||
while ((n = fscanf (fp, "system type : %256[^\n]\n", systype))
|
||||
!= EOF)
|
||||
{
|
||||
if (n == 1)
|
||||
break;
|
||||
else
|
||||
fgets (systype, 256, fp);
|
||||
}
|
||||
fclose (fp);
|
||||
|
||||
if (n == EOF)
|
||||
if (!n)
|
||||
{
|
||||
/* this can happen if the format of /proc/cpuinfo changes... */
|
||||
fprintf (stderr,
|
||||
@ -497,35 +536,23 @@ init_iosys (void)
|
||||
{
|
||||
io.sys = platform[i].io_sys;
|
||||
/* some platforms can have either EV4 or EV5 CPUs */
|
||||
if (io.sys == IOSYS_CPUDEP)
|
||||
if (io.sys == IOSYS_CPUDEP) /* SABLE or MIKASA or NORITAKE so far */
|
||||
{
|
||||
FILE * fp;
|
||||
char cputype[256];
|
||||
fp = fopen (PATH_CPUINFO, "r");
|
||||
if (fp == NULL)
|
||||
return -1;
|
||||
while ((n = fscanf (fp, "cpu model : %256[^\n]\n", cputype))
|
||||
!= EOF
|
||||
&& n != 1)
|
||||
fgets (cputype, 256, fp);
|
||||
|
||||
fclose (fp);
|
||||
|
||||
if (strcmp (platform[i].name, "Sable") == 0)
|
||||
{
|
||||
if (strncmp (cputype, "EV4", 3) == 0)
|
||||
if (strncmp (cpumodel, "EV4", 3) == 0)
|
||||
io.sys = IOSYS_T2;
|
||||
else if (strncmp (cputype, "EV5", 3) == 0)
|
||||
else if (strncmp (cpumodel, "EV5", 3) == 0)
|
||||
io.sys = IOSYS_GAMMA;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (strncmp (cputype, "EV4", 3) == 0)
|
||||
{ /* this covers MIKASA/NORITAKE */
|
||||
if (strncmp (cpumodel, "EV4", 3) == 0)
|
||||
io.sys = IOSYS_APECS;
|
||||
else if (strncmp (cputype, "EV5", 3) == 0)
|
||||
else if (strncmp (cpumodel, "EV5", 3) == 0)
|
||||
io.sys = IOSYS_CIA;
|
||||
}
|
||||
if (n == EOF || io.sys == IOSYS_CPUDEP)
|
||||
if (io.sys == IOSYS_CPUDEP)
|
||||
{
|
||||
/* This can happen if the format of /proc/cpuinfo changes.*/
|
||||
fprintf (stderr, "ioperm.init_iosys(): Unable to determine"
|
||||
@ -534,23 +561,46 @@ init_iosys (void)
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
/* some platforms can have different core logic chipsets */
|
||||
if (io.sys == IOSYS_PCIDEP) /* EB164 so far */
|
||||
{
|
||||
if (strcmp (systype, "EB164") == 0)
|
||||
{
|
||||
if (strncmp (sysvari, "RX164", 5) == 0)
|
||||
io.sys = IOSYS_POLARIS;
|
||||
else
|
||||
io.sys = IOSYS_CIA;
|
||||
}
|
||||
if (io.sys == IOSYS_PCIDEP)
|
||||
{
|
||||
/* This can happen if the format of /proc/cpuinfo changes.*/
|
||||
fprintf (stderr, "ioperm.init_iosys(): Unable to determine"
|
||||
" core logic chipset.\n");
|
||||
__set_errno (ENODEV);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
io.hae_shift = io_system[io.sys].hae_shift;
|
||||
io.bus_memory_base = io_system[io.sys].bus_memory_base;
|
||||
io.sparse_bus_memory_base = io_system[io.sys].sparse_bus_mem_base;
|
||||
io.io_base = io_system[io.sys].bus_io_base;
|
||||
|
||||
if (io.sys == IOSYS_JENSEN)
|
||||
io.swp = &ioswtch[0];
|
||||
else if (io.sys == IOSYS_TSUNAMI)
|
||||
io.swp = &ioswtch[2];
|
||||
io.swiz = IOSWIZZLE_JENSEN;
|
||||
else if (io.sys == IOSYS_TSUNAMI || io.sys == IOSYS_POLARIS)
|
||||
io.swiz = IOSWIZZLE_DENSE;
|
||||
else
|
||||
io.swp = &ioswtch[1];
|
||||
io.swiz = IOSWIZZLE_SPARSE;
|
||||
io.swp = &ioswtch[io.swiz];
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* systype is not a know platform name... */
|
||||
__set_errno (EINVAL);
|
||||
#if 1
|
||||
fprintf(stderr, "init_iosys: platform not recognized\n");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -559,18 +609,29 @@ int
|
||||
_ioperm (unsigned long int from, unsigned long int num, int turn_on)
|
||||
{
|
||||
unsigned long int addr, len;
|
||||
int prot;
|
||||
int prot, err;
|
||||
|
||||
if (!io.swp && init_iosys () < 0)
|
||||
if (!io.swp && init_iosys() < 0) {
|
||||
#if 1
|
||||
fprintf(stderr, "ioperm: init_iosys() failed\n");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* this test isn't as silly as it may look like; consider overflows! */
|
||||
if (from >= MAX_PORT || from + num > MAX_PORT)
|
||||
{
|
||||
__set_errno (EINVAL);
|
||||
#if 1
|
||||
fprintf(stderr, "ioperm: from/num out of range\n");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if 1
|
||||
fprintf(stderr, "ioperm: turn_on %d io.base %ld\n", turn_on, io.base);
|
||||
#endif
|
||||
|
||||
if (turn_on)
|
||||
{
|
||||
if (!io.base)
|
||||
@ -579,19 +640,27 @@ _ioperm (unsigned long int from, unsigned long int num, int turn_on)
|
||||
|
||||
io.hae.reg = 0; /* not used in user-level */
|
||||
io.hae.cache = 0;
|
||||
if (io.sys != IOSYS_TSUNAMI)
|
||||
if (io.swiz != IOSWIZZLE_DENSE)
|
||||
__sethae (io.hae.cache); /* synchronize with hw */
|
||||
|
||||
fd = open ("/dev/mem", O_RDWR);
|
||||
if (fd < 0)
|
||||
if (fd < 0) {
|
||||
#if 1
|
||||
fprintf(stderr, "ioperm: /dev/mem open failed\n");
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
addr = port_to_cpu_addr (0, io.sys, 1);
|
||||
len = port_to_cpu_addr (MAX_PORT, io.sys, 1) - addr;
|
||||
addr = port_to_cpu_addr (0, io.swiz, 1);
|
||||
len = port_to_cpu_addr (MAX_PORT, io.swiz, 1) - addr;
|
||||
io.base =
|
||||
(unsigned long int) __mmap (0, len, PROT_NONE, MAP_SHARED,
|
||||
fd, io.io_base);
|
||||
close (fd);
|
||||
#if 1
|
||||
fprintf(stderr, "ioperm: mmap of len 0x%lx returned 0x%lx\n",
|
||||
len, io.base);
|
||||
#endif
|
||||
if ((long) io.base == -1)
|
||||
return -1;
|
||||
}
|
||||
@ -605,10 +674,14 @@ _ioperm (unsigned long int from, unsigned long int num, int turn_on)
|
||||
/* turnoff access to relevant pages: */
|
||||
prot = PROT_NONE;
|
||||
}
|
||||
addr = port_to_cpu_addr (from, io.sys, 1);
|
||||
addr = port_to_cpu_addr (from, io.swiz, 1);
|
||||
addr &= PAGE_MASK;
|
||||
len = port_to_cpu_addr (from + num, io.sys, 1) - addr;
|
||||
return mprotect ((void *) addr, len, prot);
|
||||
len = port_to_cpu_addr (from + num, io.swiz, 1) - addr;
|
||||
err = mprotect ((void *) addr, len, prot);
|
||||
#if 1
|
||||
fprintf(stderr, "ioperm: mprotect returned %d\n", err);
|
||||
#endif
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user