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AArch64: Improve generic strlen
Improve performance by handling another 16 bytes before entering the loop. Use ADDHN in the loop to avoid SHRN+FMOV when it terminates. Change final size computation to avoid increasing latency. On Neoverse V1 performance of the random strlen benchmark improves by 4.6%. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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@ -1,4 +1,5 @@
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/* Copyright (C) 2012-2024 Free Software Foundation, Inc.
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/* Generic optimized strlen using SIMD.
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Copyright (C) 2012-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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@ -56,38 +57,52 @@ ENTRY (STRLEN)
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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fmov synd, dend
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lsr synd, synd, shift
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cbz synd, L(loop)
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cbz synd, L(next16)
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rbit synd, synd
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clz result, synd
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lsr result, result, 2
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ret
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.p2align 5
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L(loop):
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L(next16):
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ldr data, [src, 16]
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cmeq vhas_nul.16b, vdata.16b, 0
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umaxp vend.16b, vhas_nul.16b, vhas_nul.16b
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fmov synd, dend
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cbnz synd, L(loop_end)
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ldr data, [src, 32]!
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cmeq vhas_nul.16b, vdata.16b, 0
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umaxp vend.16b, vhas_nul.16b, vhas_nul.16b
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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fmov synd, dend
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cbz synd, L(loop)
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sub src, src, 16
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L(loop_end):
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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sub result, src, srcin
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fmov synd, dend
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add src, src, 16
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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add result, result, 16
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sub result, src, srcin
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clz tmp, synd
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add result, result, tmp, lsr 2
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ret
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.p2align 5
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L(loop):
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ldr data, [src, 32]!
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cmeq vhas_nul.16b, vdata.16b, 0
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addhn vend.8b, vhas_nul.8h, vhas_nul.8h
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fmov synd, dend
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cbnz synd, L(loop_end)
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ldr data, [src, 16]
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cmeq vhas_nul.16b, vdata.16b, 0
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addhn vend.8b, vhas_nul.8h, vhas_nul.8h
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fmov synd, dend
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cbz synd, L(loop)
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add src, src, 16
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L(loop_end):
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sub result, shift, src, lsl 2 /* (srcin - src) << 2. */
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#ifndef __AARCH64EB__
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rbit synd, synd
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sub result, result, 3
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#endif
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clz tmp, synd
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sub result, tmp, result
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lsr result, result, 2
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ret
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END (STRLEN)
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weak_alias (STRLEN, strlen)
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libc_hidden_builtin_def (strlen)
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