mirror of
https://sourceware.org/git/glibc.git
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x86_64: Implement evex512 version of memchr, rawmemchr and wmemchr
This patch implements following evex512 version of string functions. evex512 version takes up to 30% less cycle as compared to evex, depending on length and alignment. - memchr function using 512 bit vectors. - rawmemchr function using 512 bit vectors. - wmemchr function using 512 bit vectors. Code size data: memchr-evex.o 762 byte memchr-evex512.o 576 byte (-24%) rawmemchr-evex.o 461 byte rawmemchr-evex512.o 412 byte (-11%) wmemchr-evex.o 794 byte wmemchr-evex512.o 552 byte (-30%) Placeholder function, not used by any processor at the moment. Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
This commit is contained in:
Sunil K Pandey
parent
932dd83efd
commit
451c6e5854
@ -4,6 +4,7 @@ sysdep_routines += \
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memchr-avx2 \
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memchr-avx2-rtm \
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memchr-evex \
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memchr-evex512 \
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memchr-evex-rtm \
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memchr-sse2 \
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memcmp-avx2-movbe \
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@ -36,6 +37,7 @@ sysdep_routines += \
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rawmemchr-avx2 \
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rawmemchr-avx2-rtm \
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rawmemchr-evex \
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rawmemchr-evex512 \
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rawmemchr-evex-rtm \
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rawmemchr-sse2 \
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stpcpy-avx2 \
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@ -156,6 +158,7 @@ sysdep_routines += \
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wmemchr-avx2 \
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wmemchr-avx2-rtm \
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wmemchr-evex \
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wmemchr-evex512 \
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wmemchr-evex-rtm \
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wmemchr-sse2 \
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wmemcmp-avx2-movbe \
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@ -63,6 +63,11 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__memchr_evex)
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X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__memchr_evex512)
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X86_IFUNC_IMPL_ADD_V4 (array, i, memchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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@ -337,6 +342,11 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__rawmemchr_evex)
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X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__rawmemchr_evex512)
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X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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@ -942,6 +952,11 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__wmemchr_evex)
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X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__wmemchr_evex512)
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X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)
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304
sysdeps/x86_64/multiarch/memchr-evex-base.S
Normal file
304
sysdeps/x86_64/multiarch/memchr-evex-base.S
Normal file
@ -0,0 +1,304 @@
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/* Placeholder function, not used by any processor at the moment.
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Copyright (C) 2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* UNUSED. Exists purely as reference implementation. */
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#include <isa-level.h>
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#if ISA_SHOULD_BUILD (4)
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# include <sysdep.h>
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# ifdef USE_AS_WMEMCHR
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# define CHAR_SIZE 4
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# define VPBROADCAST vpbroadcastd
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# define VPCMPEQ vpcmpeqd
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# define VPCMPNE vpcmpneqd
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# define VPMINU vpminud
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# define VPTESTNM vptestnmd
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# else
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# define CHAR_SIZE 1
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# define VPBROADCAST vpbroadcastb
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# define VPCMPEQ vpcmpeqb
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# define VPCMPNE vpcmpneqb
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# define VPMINU vpminub
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# define VPTESTNM vptestnmb
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# endif
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# define PAGE_SIZE 4096
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# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE)
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.section SECTION(.text), "ax", @progbits
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/* Aligning entry point to 64 byte, provides better performance for
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one vector length string. */
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ENTRY_P2ALIGN (MEMCHR, 6)
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# ifndef USE_AS_RAWMEMCHR
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/* Check for zero length. */
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test %RDX_LP, %RDX_LP
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jz L(zero)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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# endif
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/* Broadcast CHAR to VMM(1). */
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VPBROADCAST %esi, %VMM(1)
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movl %edi, %eax
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andl $(PAGE_SIZE - 1), %eax
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cmpl $(PAGE_SIZE - VEC_SIZE), %eax
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ja L(page_cross)
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/* Compare [w]char for null, mask bit will be set for match. */
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VPCMPEQ (%rdi), %VMM(1), %k0
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KMOV %k0, %VRCX
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# ifndef USE_AS_RAWMEMCHR
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mov %rdx, %rsi
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/* Need to use bsfq here as upper 32 bit of rsi may zero out
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for 'bsf %ecx, %esi', if %ecx is 0. */
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bsfq %rcx, %rsi
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cmp $CHAR_PER_VEC, %rsi
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ja L(align_more)
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# ifdef USE_AS_WMEMCHR
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leaq (%rdi, %rsi, CHAR_SIZE), %rdi
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# else
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addq %rsi, %rdi
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# endif
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xor %eax, %eax
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cmp %rsi, %rdx
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cmova %rdi, %rax
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# else
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bsf %VRCX, %VRAX
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jz L(align_more)
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add %rdi, %rax
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# endif
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ret
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.p2align 5,,5
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L(page_cross):
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movl %eax, %ecx
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andl $(VEC_SIZE - 1), %ecx
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# ifdef USE_AS_WMEMCHR
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shrl $2, %ecx
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# endif
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xorq %rdi, %rax
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VPCMPEQ (PAGE_SIZE - VEC_SIZE)(%rax), %VMM(1), %k0
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KMOV %k0, %VRSI
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shr %cl, %VRSI
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# ifndef USE_AS_RAWMEMCHR
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jnz L(page_cross_end)
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movl $CHAR_PER_VEC, %eax
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sub %ecx, %eax
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cmp %rax, %rdx
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ja L(align_more)
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# else
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jz L(align_more)
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# endif
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L(page_cross_end):
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# ifndef USE_AS_RAWMEMCHR
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bsf %VRSI, %VRCX
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jz L(zero)
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leaq (%rdi, %rcx, CHAR_SIZE), %rdi
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xor %eax, %eax
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cmp %rcx, %rdx
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cmova %rdi, %rax
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# else
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bsf %VRSI, %VRAX
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add %rdi, %rax
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# endif
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ret
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# ifndef USE_AS_RAWMEMCHR
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L(zero):
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xorl %eax, %eax
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ret
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# endif
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L(ret_vec_x2):
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subq $-VEC_SIZE, %rdi
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L(ret_vec_x1):
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bsf %VRAX, %VRAX
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# ifndef USE_AS_RAWMEMCHR
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cmp %rax, %rdx
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jbe L(zero)
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# endif
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# ifdef USE_AS_WMEMCHR
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leaq (%rdi, %rax, CHAR_SIZE), %rax
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# else
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add %rdi, %rax
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# endif
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ret
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.p2align 5,,5
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L(align_more):
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# ifndef USE_AS_RAWMEMCHR
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mov %rdi, %rax
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# endif
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subq $-VEC_SIZE, %rdi
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/* Align rdi to VEC_SIZE. */
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andq $-VEC_SIZE, %rdi
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# ifndef USE_AS_RAWMEMCHR
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subq %rdi, %rax
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# ifdef USE_AS_WMEMCHR
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sar $2, %rax
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# endif
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addq %rax, %rdx
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# endif
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/* Loop unroll 4 times for 4 vector loop. */
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VPCMPEQ (%rdi), %VMM(1), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(ret_vec_x1)
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# ifndef USE_AS_RAWMEMCHR
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subq $CHAR_PER_VEC, %rdx
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jbe L(zero)
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# endif
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VPCMPEQ VEC_SIZE(%rdi), %VMM(1), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(ret_vec_x2)
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# ifndef USE_AS_RAWMEMCHR
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subq $CHAR_PER_VEC, %rdx
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jbe L(zero)
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# endif
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VPCMPEQ (VEC_SIZE * 2)(%rdi), %VMM(1), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(ret_vec_x3)
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# ifndef USE_AS_RAWMEMCHR
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subq $CHAR_PER_VEC, %rdx
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jbe L(zero)
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# endif
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VPCMPEQ (VEC_SIZE * 3)(%rdi), %VMM(1), %k0
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KMOV %k0, %VRAX
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test %VRAX, %VRAX
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jnz L(ret_vec_x4)
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# ifndef USE_AS_RAWMEMCHR
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subq $CHAR_PER_VEC, %rdx
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jbe L(zero)
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/* Save pointer to find alignment adjustment. */
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movq %rdi, %rax
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# endif
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/* Align address to VEC_SIZE * 4 for loop. */
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andq $-(VEC_SIZE * 4), %rdi
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/* Add alignment difference to rdx. */
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# ifndef USE_AS_RAWMEMCHR
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subq %rdi, %rax
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# ifdef USE_AS_WMEMCHR
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shr $2, %VRAX
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# endif
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addq %rax, %rdx
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# endif
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/* 4 vector loop. */
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.p2align 5,,11
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L(loop):
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VPCMPNE (VEC_SIZE * 4)(%rdi), %VMM(1), %k1
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vpxorq (VEC_SIZE * 5)(%rdi), %VMM(1), %VMM(2)
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vpxorq (VEC_SIZE * 6)(%rdi), %VMM(1), %VMM(3)
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VPCMPEQ (VEC_SIZE * 7)(%rdi), %VMM(1), %k3
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VPMINU %VMM(2), %VMM(3), %VMM(3){%k1}{z}
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VPTESTNM %VMM(3), %VMM(3), %k2
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subq $-(VEC_SIZE * 4), %rdi
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KORTEST %k2, %k3
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# ifdef USE_AS_RAWMEMCHR
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jz L(loop)
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# else
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jnz L(loopend)
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subq $(CHAR_PER_VEC * 4), %rdx
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ja L(loop)
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L(zero_2):
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xor %eax, %eax
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ret
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# endif
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L(loopend):
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VPCMPEQ (%rdi), %VMM(1), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(ret_vec_x1)
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# ifndef USE_AS_RAWMEMCHR
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subq $CHAR_PER_VEC, %rdx
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jbe L(zero_2)
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# endif
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VPCMPEQ VEC_SIZE(%rdi), %VMM(1), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(ret_vec_x2)
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# ifndef USE_AS_RAWMEMCHR
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subq $CHAR_PER_VEC, %rdx
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jbe L(zero_2)
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# endif
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VPCMPEQ (VEC_SIZE * 2)(%rdi), %VMM(1), %k1
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KMOV %k1, %VRAX
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test %VRAX, %VRAX
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jnz L(ret_vec_x3)
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# ifndef USE_AS_RAWMEMCHR
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subq $CHAR_PER_VEC, %rdx
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jbe L(zero_2)
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# endif
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/* At this point null [w]char must be in the fourth vector so no
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need to check. */
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KMOV %k3, %VRAX
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L(ret_vec_x4):
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bsf %VRAX, %VRAX
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# ifndef USE_AS_RAWMEMCHR
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cmp %rax, %rdx
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jbe L(zero)
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# endif
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leaq (VEC_SIZE * 3)(%rdi, %rax, CHAR_SIZE), %rax
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ret
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.p2align 5,,5
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L(ret_vec_x3):
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bsf %VRAX, %VRAX
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# ifndef USE_AS_RAWMEMCHR
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cmp %rax, %rdx
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jbe L(zero)
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# endif
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leaq (VEC_SIZE * 2)(%rdi, %rax, CHAR_SIZE), %rax
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ret
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END (MEMCHR)
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#endif
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8
sysdeps/x86_64/multiarch/memchr-evex512.S
Normal file
8
sysdeps/x86_64/multiarch/memchr-evex512.S
Normal file
@ -0,0 +1,8 @@
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# ifndef MEMCHR
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# define MEMCHR __memchr_evex512
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# endif
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#include "x86-evex512-vecs.h"
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#include "reg-macros.h"
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#include "memchr-evex-base.S"
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7
sysdeps/x86_64/multiarch/rawmemchr-evex512.S
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7
sysdeps/x86_64/multiarch/rawmemchr-evex512.S
Normal file
@ -0,0 +1,7 @@
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#ifndef RAWMEMCHR
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# define RAWMEMCHR __rawmemchr_evex512
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#endif
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#define USE_AS_RAWMEMCHR 1
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#define MEMCHR RAWMEMCHR
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#include "memchr-evex512.S"
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9
sysdeps/x86_64/multiarch/wmemchr-evex512.S
Normal file
9
sysdeps/x86_64/multiarch/wmemchr-evex512.S
Normal file
@ -0,0 +1,9 @@
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#ifndef WMEMCHR
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# define WMEMCHR __wmemchr_evex512
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#endif
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#define MEMCHR WMEMCHR
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#define USE_AS_WMEMCHR 1
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#define USE_WIDE_CHAR 1
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#include "memchr-evex512.S"
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