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powerpc: Restrict xssqrtqp operands to Vector Registers (bug 21941)
POWER ISA 3.0 introduces the xssqrtqp instructions, which expects operands to be in Vector Registers (Altivec/VMX), even though this instruction belongs to the Vector-Scalar Instruction Set. In GCC's Extended Assembly for POWER, the 'wq' register constraint is provided for use with IEEE 754 128-bit floating-point values. However, this constraint does not limit the register allocation to Vector Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX) to the operands of the instruction. This patch changes the register constraint used in sqrtf128 from 'wq' to 'v', in order to request a Vector Register (Altivec/VMX) for use with the xssqrtqp instruction. Tested for powerpc64le and --with-cpu=power9. [BZ #21941] * sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since xssqrtqp requires operands to be in Vector Registers (Altivec/VMX), replace the register constraint 'wq' with 'v'. * sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c (__ieee754_sqrtf128): Likewise.
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@ -1,3 +1,12 @@
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2017-08-10 Gabriel F. T. Gomes <gftg@linux.vnet.ibm.com>
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[BZ #21941]
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* sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since
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xssqrtqp requires operands to be in Vector Registers
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(Altivec/VMX), replace the register constraint 'wq' with 'v'.
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* sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
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(__ieee754_sqrtf128): Likewise.
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2017-08-10 Wilco Dijkstra <wdijkstr@arm.com>
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* sysdeps/aarch64/memcmp.S (memcmp):
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@ -30,7 +30,7 @@ extern __always_inline _Float128
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__ieee754_sqrtf128 (_Float128 __x)
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{
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_Float128 __z;
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asm ("xssqrtqp %0,%1" : "=wq" (__z) : "wq" (__x));
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asm ("xssqrtqp %0,%1" : "=v" (__z) : "v" (__x));
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return __z;
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}
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#endif
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@ -30,7 +30,7 @@ __float128
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__ieee754_sqrtf128 (__float128 a)
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{
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__float128 z;
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asm ("xssqrtqp %0,%1" : "=wq" (z) : "wq" (a));
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asm ("xssqrtqp %0,%1" : "=v" (z) : "v" (a));
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return z;
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}
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strong_alias (__ieee754_sqrtf128, __sqrtf128_finite)
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