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Define bit_XXX and index_XXX.

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This patch defines bit_XXX and index_XXX and use them to check processor
feature in assembly code.  It can prevent typos in processor feature
check.
This commit is contained in:
H.J. Lu 2009-12-13 09:47:02 -08:00 committed by Ulrich Drepper
parent 9b2f1d4b58
commit 51ddd2c01e
10 changed files with 50 additions and 17 deletions
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19
ChangeLog
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@ -1,3 +1,22 @@
2009-12-09 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86_64/multiarch/init-arch.h: Include <ifunc-defines.h>
if __ASSEMBLER__ is defined.
(bit_SSSE3): New. Defined for __ASSEMBLER__.
(bit_SSE4_2): Likewise.
(index_SSSE3): Likewise.
(index_SSE4_2): Likewise.
* sysdeps/x86_64/multiarch/rawmemchr.S: Include <init-arch.h>
instead of <ifunc-defines.h>. Use bit_XXX and index_XXX to
check processor feature.
* sysdeps/x86_64/multiarch/strchr.S: Likewise.
* sysdeps/x86_64/multiarch/strcmp.S: Likewise.
* sysdeps/x86_64/multiarch/strcpy.S: Likewise.
* sysdeps/x86_64/multiarch/strcspn.S: Likewise.
* sysdeps/x86_64/multiarch/strlen.S: Likewise.
* sysdeps/x86_64/multiarch/strrchr.S: Likewise.
* sysdeps/x86_64/multiarch/strspn.S: Likewise.
2009-12-08 Kaz Kojima <kkojima@rr.iij4u.or.jp>
* sysdeps/sh/elf/initfini.c: Update according to generic/initfini.c.

14
sysdeps/x86_64/multiarch/init-arch.h
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@ -16,6 +16,18 @@
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
#ifdef __ASSEMBLER__
#include <ifunc-defines.h>
#define bit_SSSE3 (1 << 9)
#define bit_SSE4_2 (1 << 20)
#define index_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
#define index_SSE4_2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET
#else /* __ASSEMBLER__ */
#include <sys/param.h>
enum
@ -71,3 +83,5 @@ extern const struct cpu_features *__get_cpu_features (void)
#define HAS_POPCOUNT HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 23)
#define HAS_SSE4_2 HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 20)
#define HAS_FMA HAS_CPU_FEATURE (COMMON_CPUID_INDEX_1, ecx, 12)
#endif /* __ASSEMBLER__ */

4
sysdeps/x86_64/multiarch/rawmemchr.S
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@ -18,7 +18,7 @@
02111-1307 USA. */
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
/* Define multiple versions only for the definition in lib. */
@ -30,7 +30,7 @@ ENTRY(rawmemchr)
jne 1f
call __init_cpu_features
1: leaq __rawmemchr_sse2(%rip), %rax
testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __rawmemchr_sse42(%rip), %rax
2: ret

4
sysdeps/x86_64/multiarch/strchr.S
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@ -18,7 +18,7 @@
02111-1307 USA. */
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
/* Define multiple versions only for the definition in libc. */
@ -30,7 +30,7 @@ ENTRY(strchr)
jne 1f
call __init_cpu_features
1: leaq __strchr_sse2(%rip), %rax
testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __strchr_sse42(%rip), %rax
2: ret

6
sysdeps/x86_64/multiarch/strcmp.S
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@ -19,7 +19,7 @@
02111-1307 USA. */
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
#ifdef USE_AS_STRNCMP
/* Since the counter, %r11, is unsigned, we branch to strcmp_exitz
@ -64,10 +64,10 @@ ENTRY(STRCMP)
call __init_cpu_features
1:
leaq STRCMP_SSE42(%rip), %rax
testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jnz 2f
leaq STRCMP_SSSE3(%rip), %rax
testl $(1<<9), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip)
jnz 2f
leaq STRCMP_SSE2(%rip), %rax
2: ret

4
sysdeps/x86_64/multiarch/strcpy.S
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@ -19,7 +19,7 @@
02111-1307 USA. */
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
#if !defined (USE_AS_STPCPY) && !defined (USE_AS_STRNCPY)
# ifndef STRCPY
@ -63,7 +63,7 @@ ENTRY(STRCPY)
jne 1f
call __init_cpu_features
1: leaq STRCPY_SSE2(%rip), %rax
testl $(1<<9), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip)
jz 2f
leaq STRCPY_SSSE3(%rip), %rax
2: ret

4
sysdeps/x86_64/multiarch/strcspn.S
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@ -23,7 +23,7 @@
#ifdef HAVE_SSE4_SUPPORT
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
#ifdef USE_AS_STRPBRK
#define STRCSPN_SSE42 __strpbrk_sse42
@ -49,7 +49,7 @@ ENTRY(STRCSPN)
jne 1f
call __init_cpu_features
1: leaq STRCSPN_SSE2(%rip), %rax
testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq STRCSPN_SSE42(%rip), %rax
2: ret

4
sysdeps/x86_64/multiarch/strlen.S
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@ -19,7 +19,7 @@
02111-1307 USA. */
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
/* Define multiple versions only for the definition in libc and for
@ -33,7 +33,7 @@ ENTRY(strlen)
jne 1f
call __init_cpu_features
1: leaq __strlen_sse2(%rip), %rax
testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __strlen_sse42(%rip), %rax
2: ret

4
sysdeps/x86_64/multiarch/strrchr.S
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@ -18,7 +18,7 @@
02111-1307 USA. */
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
/* Define multiple versions only for the definition in libc and for
@ -32,7 +32,7 @@ ENTRY(strrchr)
jne 1f
call __init_cpu_features
1: leaq __strrchr_sse2(%rip), %rax
testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __strrchr_sse42(%rip), %rax
2: ret

4
sysdeps/x86_64/multiarch/strspn.S
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@ -23,7 +23,7 @@
#ifdef HAVE_SSE4_SUPPORT
#include <sysdep.h>
#include <ifunc-defines.h>
#include <init-arch.h>
/* Define multiple versions only for the definition in libc. */
#ifndef NOT_IN_libc
@ -34,7 +34,7 @@ ENTRY(strspn)
jne 1f
call __init_cpu_features
1: leaq __strspn_sse2(%rip), %rax
testl $(1<<20), __cpu_features+CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET(%rip)
testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
jz 2f
leaq __strspn_sse42(%rip), %rax
2: ret