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x86: Improve vec generation in memset-vec-unaligned-erms.S
No bug.
Split vec generation into multiple steps. This allows the
broadcast in AVX2 to use 'xmm' registers for the L(less_vec)
case. This saves an expensive lane-cross instruction and removes
the need for 'vzeroupper'.
For SSE2 replace 2x 'punpck' instructions with zero-idiom 'pxor' for
byte broadcast.
Results for memset-avx2 small (geomean of N = 20 benchset runs).
size, New Time, Old Time, New / Old
0, 4.100, 3.831, 0.934
1, 5.074, 4.399, 0.867
2, 4.433, 4.411, 0.995
4, 4.487, 4.415, 0.984
8, 4.454, 4.396, 0.987
16, 4.502, 4.443, 0.987
All relevant string/wcsmbs tests are passing.
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
(cherry picked from commit b62ace2740)
This commit is contained in:
Noah Goldstein
Sunil K Pandey
parent
36766c02af
commit
58596411ad
@ -28,17 +28,22 @@
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#define VMOVU movups
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#define VMOVA movaps
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#define MEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \
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# define MEMSET_SET_VEC0_AND_SET_RETURN(d, r) \
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movd d, %xmm0; \
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movq r, %rax; \
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punpcklbw %xmm0, %xmm0; \
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punpcklwd %xmm0, %xmm0; \
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pshufd $0, %xmm0, %xmm0
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pxor %xmm1, %xmm1; \
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pshufb %xmm1, %xmm0; \
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movq r, %rax
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#define WMEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \
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# define WMEMSET_SET_VEC0_AND_SET_RETURN(d, r) \
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movd d, %xmm0; \
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movq r, %rax; \
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pshufd $0, %xmm0, %xmm0
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pshufd $0, %xmm0, %xmm0; \
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movq r, %rax
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# define MEMSET_VDUP_TO_VEC0_HIGH()
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# define MEMSET_VDUP_TO_VEC0_LOW()
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# define WMEMSET_VDUP_TO_VEC0_HIGH()
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# define WMEMSET_VDUP_TO_VEC0_LOW()
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#define SECTION(p) p
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@ -10,15 +10,18 @@
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# define VMOVU vmovdqu
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# define VMOVA vmovdqa
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# define MEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \
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# define MEMSET_SET_VEC0_AND_SET_RETURN(d, r) \
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vmovd d, %xmm0; \
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movq r, %rax; \
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vpbroadcastb %xmm0, %ymm0
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movq r, %rax;
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# define WMEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \
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vmovd d, %xmm0; \
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movq r, %rax; \
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vpbroadcastd %xmm0, %ymm0
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# define WMEMSET_SET_VEC0_AND_SET_RETURN(d, r) \
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MEMSET_SET_VEC0_AND_SET_RETURN(d, r)
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# define MEMSET_VDUP_TO_VEC0_HIGH() vpbroadcastb %xmm0, %ymm0
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# define MEMSET_VDUP_TO_VEC0_LOW() vpbroadcastb %xmm0, %xmm0
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# define WMEMSET_VDUP_TO_VEC0_HIGH() vpbroadcastd %xmm0, %ymm0
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# define WMEMSET_VDUP_TO_VEC0_LOW() vpbroadcastd %xmm0, %xmm0
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# ifndef SECTION
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# define SECTION(p) p##.avx
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@ -30,5 +33,6 @@
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# define WMEMSET_SYMBOL(p,s) p##_avx2_##s
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# endif
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# define USE_XMM_LESS_VEC
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# include "memset-vec-unaligned-erms.S"
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#endif
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@ -15,13 +15,19 @@
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# define VZEROUPPER
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# define MEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \
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movq r, %rax; \
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vpbroadcastb d, %VEC0
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# define MEMSET_SET_VEC0_AND_SET_RETURN(d, r) \
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vpbroadcastb d, %VEC0; \
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movq r, %rax
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# define WMEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \
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movq r, %rax; \
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vpbroadcastd d, %VEC0
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# define WMEMSET_SET_VEC0_AND_SET_RETURN(d, r) \
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vpbroadcastd d, %VEC0; \
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movq r, %rax
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# define MEMSET_VDUP_TO_VEC0_HIGH()
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# define MEMSET_VDUP_TO_VEC0_LOW()
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# define WMEMSET_VDUP_TO_VEC0_HIGH()
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# define WMEMSET_VDUP_TO_VEC0_LOW()
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# define SECTION(p) p##.evex512
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# define MEMSET_SYMBOL(p,s) p##_avx512_##s
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@ -15,13 +15,19 @@
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# define VZEROUPPER
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# define MEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \
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movq r, %rax; \
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vpbroadcastb d, %VEC0
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# define MEMSET_SET_VEC0_AND_SET_RETURN(d, r) \
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vpbroadcastb d, %VEC0; \
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movq r, %rax
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# define WMEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \
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movq r, %rax; \
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vpbroadcastd d, %VEC0
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# define WMEMSET_SET_VEC0_AND_SET_RETURN(d, r) \
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vpbroadcastd d, %VEC0; \
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movq r, %rax
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# define MEMSET_VDUP_TO_VEC0_HIGH()
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# define MEMSET_VDUP_TO_VEC0_LOW()
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# define WMEMSET_VDUP_TO_VEC0_HIGH()
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# define WMEMSET_VDUP_TO_VEC0_LOW()
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# define SECTION(p) p##.evex
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# define MEMSET_SYMBOL(p,s) p##_evex_##s
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@ -58,8 +58,10 @@
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#ifndef MOVQ
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# if VEC_SIZE > 16
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# define MOVQ vmovq
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# define MOVD vmovd
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# else
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# define MOVQ movq
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# define MOVD movd
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# endif
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#endif
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@ -72,9 +74,17 @@
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#if defined USE_WITH_EVEX || defined USE_WITH_AVX512
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# define END_REG rcx
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# define LOOP_REG rdi
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# define LESS_VEC_REG rax
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#else
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# define END_REG rdi
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# define LOOP_REG rdx
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# define LESS_VEC_REG rdi
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#endif
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#ifdef USE_XMM_LESS_VEC
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# define XMM_SMALL 1
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#else
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# define XMM_SMALL 0
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#endif
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#define PAGE_SIZE 4096
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@ -110,8 +120,12 @@ END_CHK (WMEMSET_CHK_SYMBOL (__wmemset_chk, unaligned))
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ENTRY (WMEMSET_SYMBOL (__wmemset, unaligned))
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shl $2, %RDX_LP
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WMEMSET_VDUP_TO_VEC0_AND_SET_RETURN (%esi, %rdi)
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jmp L(entry_from_bzero)
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WMEMSET_SET_VEC0_AND_SET_RETURN (%esi, %rdi)
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WMEMSET_VDUP_TO_VEC0_LOW()
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cmpq $VEC_SIZE, %rdx
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jb L(less_vec_no_vdup)
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WMEMSET_VDUP_TO_VEC0_HIGH()
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jmp L(entry_from_wmemset)
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END (WMEMSET_SYMBOL (__wmemset, unaligned))
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#endif
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@ -123,7 +137,7 @@ END_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned))
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#endif
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ENTRY (MEMSET_SYMBOL (__memset, unaligned))
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MEMSET_VDUP_TO_VEC0_AND_SET_RETURN (%esi, %rdi)
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MEMSET_SET_VEC0_AND_SET_RETURN (%esi, %rdi)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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mov %edx, %edx
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@ -131,6 +145,8 @@ ENTRY (MEMSET_SYMBOL (__memset, unaligned))
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L(entry_from_bzero):
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cmpq $VEC_SIZE, %rdx
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jb L(less_vec)
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MEMSET_VDUP_TO_VEC0_HIGH()
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L(entry_from_wmemset):
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cmpq $(VEC_SIZE * 2), %rdx
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ja L(more_2x_vec)
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/* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */
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@ -179,27 +195,27 @@ END_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned_erms))
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# endif
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ENTRY_P2ALIGN (MEMSET_SYMBOL (__memset, unaligned_erms), 6)
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MEMSET_VDUP_TO_VEC0_AND_SET_RETURN (%esi, %rdi)
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MEMSET_SET_VEC0_AND_SET_RETURN (%esi, %rdi)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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mov %edx, %edx
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# endif
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cmp $VEC_SIZE, %RDX_LP
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jb L(less_vec)
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MEMSET_VDUP_TO_VEC0_HIGH ()
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cmp $(VEC_SIZE * 2), %RDX_LP
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ja L(stosb_more_2x_vec)
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/* From VEC and to 2 * VEC. No branch when size == VEC_SIZE.
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*/
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VMOVU %VEC(0), (%rax)
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VMOVU %VEC(0), -VEC_SIZE(%rax, %rdx)
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/* From VEC and to 2 * VEC. No branch when size == VEC_SIZE. */
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VMOVU %VEC(0), (%rdi)
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VMOVU %VEC(0), (VEC_SIZE * -1)(%rdi, %rdx)
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VZEROUPPER_RETURN
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#endif
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.p2align 4,, 10
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.p2align 4,, 4
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L(last_2x_vec):
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#ifdef USE_LESS_VEC_MASK_STORE
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VMOVU %VEC(0), (VEC_SIZE * 2 + LOOP_4X_OFFSET)(%rcx)
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VMOVU %VEC(0), (VEC_SIZE * 3 + LOOP_4X_OFFSET)(%rcx)
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VMOVU %VEC(0), (VEC_SIZE * -2)(%rdi, %rdx)
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VMOVU %VEC(0), (VEC_SIZE * -1)(%rdi, %rdx)
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#else
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VMOVU %VEC(0), (VEC_SIZE * -2)(%rdi)
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VMOVU %VEC(0), (VEC_SIZE * -1)(%rdi)
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@ -212,6 +228,7 @@ L(last_2x_vec):
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#ifdef USE_LESS_VEC_MASK_STORE
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.p2align 4,, 10
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L(less_vec):
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L(less_vec_no_vdup):
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/* Less than 1 VEC. */
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# if VEC_SIZE != 16 && VEC_SIZE != 32 && VEC_SIZE != 64
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# error Unsupported VEC_SIZE!
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@ -262,28 +279,18 @@ L(stosb_more_2x_vec):
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/* Fallthrough goes to L(loop_4x_vec). Tests for memset (2x, 4x]
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and (4x, 8x] jump to target. */
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L(more_2x_vec):
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/* Two different methods of setting up pointers / compare. The
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two methods are based on the fact that EVEX/AVX512 mov
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instructions take more bytes then AVX2/SSE2 mov instructions. As
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well that EVEX/AVX512 machines also have fast LEA_BID. Both
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setup and END_REG to avoid complex address mode. For EVEX/AVX512
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this saves code size and keeps a few targets in one fetch block.
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For AVX2/SSE2 this helps prevent AGU bottlenecks. */
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#if defined USE_WITH_EVEX || defined USE_WITH_AVX512
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/* If EVEX/AVX512 compute END_REG - (VEC_SIZE * 4 +
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LOOP_4X_OFFSET) with LEA_BID. */
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/* END_REG is rcx for EVEX/AVX512. */
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leaq -(VEC_SIZE * 4 + LOOP_4X_OFFSET)(%rdi, %rdx), %END_REG
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#endif
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/* Stores to first 2x VEC before cmp as any path forward will
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require it. */
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VMOVU %VEC(0), (%rax)
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VMOVU %VEC(0), VEC_SIZE(%rax)
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/* Store next 2x vec regardless. */
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VMOVU %VEC(0), (%rdi)
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VMOVU %VEC(0), (VEC_SIZE * 1)(%rdi)
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/* Two different methods of setting up pointers / compare. The two
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methods are based on the fact that EVEX/AVX512 mov instructions take
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more bytes then AVX2/SSE2 mov instructions. As well that EVEX/AVX512
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machines also have fast LEA_BID. Both setup and END_REG to avoid complex
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address mode. For EVEX/AVX512 this saves code size and keeps a few
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targets in one fetch block. For AVX2/SSE2 this helps prevent AGU
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bottlenecks. */
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#if !(defined USE_WITH_EVEX || defined USE_WITH_AVX512)
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/* If AVX2/SSE2 compute END_REG (rdi) with ALU. */
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addq %rdx, %END_REG
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@ -292,6 +299,15 @@ L(more_2x_vec):
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cmpq $(VEC_SIZE * 4), %rdx
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jbe L(last_2x_vec)
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#if defined USE_WITH_EVEX || defined USE_WITH_AVX512
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/* If EVEX/AVX512 compute END_REG - (VEC_SIZE * 4 + LOOP_4X_OFFSET) with
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LEA_BID. */
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/* END_REG is rcx for EVEX/AVX512. */
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leaq -(VEC_SIZE * 4 + LOOP_4X_OFFSET)(%rdi, %rdx), %END_REG
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#endif
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/* Store next 2x vec regardless. */
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VMOVU %VEC(0), (VEC_SIZE * 2)(%rax)
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VMOVU %VEC(0), (VEC_SIZE * 3)(%rax)
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@ -355,65 +371,93 @@ L(stosb_local):
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/* Define L(less_vec) only if not otherwise defined. */
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.p2align 4
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L(less_vec):
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/* Broadcast esi to partial register (i.e VEC_SIZE == 32 broadcast to
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xmm). This is only does anything for AVX2. */
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MEMSET_VDUP_TO_VEC0_LOW ()
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L(less_vec_no_vdup):
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#endif
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L(cross_page):
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#if VEC_SIZE > 32
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cmpl $32, %edx
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jae L(between_32_63)
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jge L(between_32_63)
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#endif
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#if VEC_SIZE > 16
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cmpl $16, %edx
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jae L(between_16_31)
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jge L(between_16_31)
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#endif
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#ifndef USE_XMM_LESS_VEC
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MOVQ %XMM0, %rcx
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#endif
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MOVQ %XMM0, %rdi
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cmpl $8, %edx
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jae L(between_8_15)
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jge L(between_8_15)
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cmpl $4, %edx
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jae L(between_4_7)
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jge L(between_4_7)
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cmpl $1, %edx
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ja L(between_2_3)
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jb L(return)
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movb %sil, (%rax)
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VZEROUPPER_RETURN
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jg L(between_2_3)
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jl L(between_0_0)
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movb %sil, (%LESS_VEC_REG)
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L(between_0_0):
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ret
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/* Align small targets only if not doing so would cross a fetch
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line. */
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/* Align small targets only if not doing so would cross a fetch line.
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*/
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#if VEC_SIZE > 32
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.p2align 4,, SMALL_MEMSET_ALIGN(MOV_SIZE, RET_SIZE)
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/* From 32 to 63. No branch when size == 32. */
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L(between_32_63):
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VMOVU %YMM0, (%rax)
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VMOVU %YMM0, -32(%rax, %rdx)
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VMOVU %YMM0, (%LESS_VEC_REG)
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VMOVU %YMM0, -32(%LESS_VEC_REG, %rdx)
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VZEROUPPER_RETURN
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#endif
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#if VEC_SIZE >= 32
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.p2align 4,, SMALL_MEMSET_ALIGN(MOV_SIZE, RET_SIZE)
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.p2align 4,, SMALL_MEMSET_ALIGN(MOV_SIZE, 1)
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L(between_16_31):
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/* From 16 to 31. No branch when size == 16. */
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VMOVU %XMM0, (%rax)
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VMOVU %XMM0, -16(%rax, %rdx)
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VZEROUPPER_RETURN
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VMOVU %XMM0, (%LESS_VEC_REG)
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VMOVU %XMM0, -16(%LESS_VEC_REG, %rdx)
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ret
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#endif
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.p2align 4,, SMALL_MEMSET_ALIGN(3, RET_SIZE)
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/* Move size is 3 for SSE2, EVEX, and AVX512. Move size is 4 for AVX2.
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*/
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.p2align 4,, SMALL_MEMSET_ALIGN(3 + XMM_SMALL, 1)
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L(between_8_15):
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/* From 8 to 15. No branch when size == 8. */
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movq %rdi, (%rax)
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movq %rdi, -8(%rax, %rdx)
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VZEROUPPER_RETURN
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#ifdef USE_XMM_LESS_VEC
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MOVQ %XMM0, (%rdi)
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MOVQ %XMM0, -8(%rdi, %rdx)
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#else
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movq %rcx, (%LESS_VEC_REG)
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movq %rcx, -8(%LESS_VEC_REG, %rdx)
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#endif
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ret
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.p2align 4,, SMALL_MEMSET_ALIGN(2, RET_SIZE)
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/* Move size is 2 for SSE2, EVEX, and AVX512. Move size is 4 for AVX2.
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*/
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.p2align 4,, SMALL_MEMSET_ALIGN(2 << XMM_SMALL, 1)
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L(between_4_7):
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/* From 4 to 7. No branch when size == 4. */
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movl %edi, (%rax)
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movl %edi, -4(%rax, %rdx)
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VZEROUPPER_RETURN
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#ifdef USE_XMM_LESS_VEC
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MOVD %XMM0, (%rdi)
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MOVD %XMM0, -4(%rdi, %rdx)
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#else
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movl %ecx, (%LESS_VEC_REG)
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movl %ecx, -4(%LESS_VEC_REG, %rdx)
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#endif
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ret
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.p2align 4,, SMALL_MEMSET_ALIGN(3, RET_SIZE)
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/* 4 * XMM_SMALL for the third mov for AVX2. */
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.p2align 4,, 4 * XMM_SMALL + SMALL_MEMSET_ALIGN(3, 1)
|
||||
L(between_2_3):
|
||||
/* From 2 to 3. No branch when size == 2. */
|
||||
movw %di, (%rax)
|
||||
movb %dil, -1(%rax, %rdx)
|
||||
VZEROUPPER_RETURN
|
||||
#ifdef USE_XMM_LESS_VEC
|
||||
movb %sil, (%rdi)
|
||||
movb %sil, 1(%rdi)
|
||||
movb %sil, -1(%rdi, %rdx)
|
||||
#else
|
||||
movw %cx, (%LESS_VEC_REG)
|
||||
movb %sil, -1(%LESS_VEC_REG, %rdx)
|
||||
#endif
|
||||
ret
|
||||
END (MEMSET_SYMBOL (__memset, unaligned_erms))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user