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x86: Optimizing memcpy for AMD Zen architecture.
Modifying the shareable cache '__x86_shared_cache_size', which is a factor in computing the non-temporal threshold parameter '__x86_shared_non_temporal_threshold' to optimize memcpy for AMD Zen architectures. In the existing implementation, the shareable cache is computed as 'L3 per thread, L2 per core'. Recomputing this shareable cache as 'L3 per CCX(Core-Complex)' has brought in performance gains. As per the large bench variant results, this patch also addresses the regression problem on AMD Zen architectures. Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>
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@ -320,7 +320,7 @@ init_cacheinfo (void)
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threads = 1 << ((ecx >> 12) & 0x0f);
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}
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if (threads == 0)
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if (threads == 0 || cpu_features->basic.family >= 0x17)
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{
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/* If APIC ID width is not available, use logical
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processor count. */
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@ -335,13 +335,30 @@ init_cacheinfo (void)
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if (threads > 0)
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shared /= threads;
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/* Account for exclusive L2 and L3 caches. */
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shared += core;
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}
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/* Get shared cache per ccx for Zen architectures. */
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if (cpu_features->basic.family >= 0x17)
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{
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unsigned int eax;
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/* Get number of threads share the L3 cache in CCX. */
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__cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);
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unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;
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shared *= threads_per_ccx;
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}
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else
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{
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/* Account for exclusive L2 and L3 caches. */
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shared += core;
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}
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}
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}
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if (cpu_features->data_cache_size != 0)
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data = cpu_features->data_cache_size;
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{
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if (data == 0 || cpu_features->basic.kind != arch_kind_amd)
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data = cpu_features->data_cache_size;
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}
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if (data > 0)
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{
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@ -354,7 +371,10 @@ init_cacheinfo (void)
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}
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if (cpu_features->shared_cache_size != 0)
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shared = cpu_features->shared_cache_size;
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{
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if (shared == 0 || cpu_features->basic.kind != arch_kind_amd)
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shared = cpu_features->shared_cache_size;
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}
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if (shared > 0)
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{
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