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https://sourceware.org/git/glibc.git
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x86_64: Implement evex512 version of strchrnul, strchr and wcschr
This patch implements following evex512 version of string functions. evex512 version takes up to 30% less cycle as compared to evex, depending on length and alignment. - strchrnul function using 512 bit vectors. - strchr function using 512 bit vectors. - wcschr function using 512 bit vectors. Code size data: strchrnul-evex.o 599 byte strchrnul-evex512.o 569 byte (-5%) strchr-evex.o 639 byte strchr-evex512.o 595 byte (-7%) wcschr-evex.o 644 byte wcschr-evex512.o 607 byte (-6%) Placeholder function, not used by any processor at the moment. Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
This commit is contained in:
Sunil K Pandey
parent
7a6ca82f80
commit
59e501f204
@ -62,11 +62,13 @@ sysdep_routines += \
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strchr-avx2 \
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strchr-avx2-rtm \
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strchr-evex \
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strchr-evex512 \
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strchr-sse2 \
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strchr-sse2-no-bsf \
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strchrnul-avx2 \
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strchrnul-avx2-rtm \
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strchrnul-evex \
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strchrnul-evex512 \
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strchrnul-sse2 \
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strcmp-avx2 \
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strcmp-avx2-rtm \
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@ -131,6 +133,7 @@ sysdep_routines += \
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wcschr-avx2 \
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wcschr-avx2-rtm \
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wcschr-evex \
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wcschr-evex512 \
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wcschr-sse2 \
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wcscmp-avx2 \
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wcscmp-avx2-rtm \
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@ -544,6 +544,10 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__strchr_evex)
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X86_IFUNC_IMPL_ADD_V4 (array, i, strchr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)),
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__strchr_evex512)
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X86_IFUNC_IMPL_ADD_V3 (array, i, strchr,
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(CPU_FEATURE_USABLE (AVX2)
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&& CPU_FEATURE_USABLE (BMI2)),
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@ -569,6 +573,10 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__strchrnul_evex)
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X86_IFUNC_IMPL_ADD_V4 (array, i, strchrnul,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)),
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__strchrnul_evex512)
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X86_IFUNC_IMPL_ADD_V3 (array, i, strchrnul,
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(CPU_FEATURE_USABLE (AVX2)
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&& CPU_FEATURE_USABLE (BMI2)),
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@ -793,6 +801,10 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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&& CPU_FEATURE_USABLE (AVX512BW)
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&& CPU_FEATURE_USABLE (BMI2)),
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__wcschr_evex)
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X86_IFUNC_IMPL_ADD_V4 (array, i, wcschr,
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(CPU_FEATURE_USABLE (AVX512VL)
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&& CPU_FEATURE_USABLE (AVX512BW)),
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__wcschr_evex512)
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X86_IFUNC_IMPL_ADD_V3 (array, i, wcschr,
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(CPU_FEATURE_USABLE (AVX2)
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&& CPU_FEATURE_USABLE (BMI2)),
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282
sysdeps/x86_64/multiarch/strchr-evex-base.S
Normal file
282
sysdeps/x86_64/multiarch/strchr-evex-base.S
Normal file
@ -0,0 +1,282 @@
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/* Placeholder function, not used by any processor at the moment.
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Copyright (C) 2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* UNUSED. Exists purely as reference implementation. */
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#include <isa-level.h>
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#if ISA_SHOULD_BUILD (4)
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# include <sysdep.h>
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# ifdef USE_AS_WCSCHR
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# define CHAR_REG esi
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# define CHAR_SIZE 4
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# define VPBROADCAST vpbroadcastd
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# define VPCMP vpcmpd
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# define VPCMPNE vpcmpneqd
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# define VPMINU vpminud
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# define VPTEST vptestmd
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# define VPTESTN vptestnmd
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# else
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# define CHAR_REG sil
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# define CHAR_SIZE 1
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# define VPBROADCAST vpbroadcastb
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# define VPCMP vpcmpb
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# define VPCMPNE vpcmpneqb
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# define VPMINU vpminub
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# define VPTEST vptestmb
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# define VPTESTN vptestnmb
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# endif
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# define PAGE_SIZE 4096
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# define CHAR_PER_VEC (VEC_SIZE / CHAR_SIZE)
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# define VEC_MATCH_MASK ((1 << CHAR_PER_VEC) - 1)
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.section SECTION(.text), "ax", @progbits
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/* Aligning entry point to 64 byte, provides better performance for
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one vector length string. */
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ENTRY_P2ALIGN (STRCHR, 6)
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/* Broadcast CHAR to VMM(0). */
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VPBROADCAST %esi, %VMM(0)
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movl %edi, %eax
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sall $20,%eax
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cmpl $((PAGE_SIZE - VEC_SIZE) << 20), %eax
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ja L(page_cross)
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VMOVU (%rdi), %VMM(1)
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VPCMPNE %VMM(1), %VMM(0), %k1
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VPTEST %VMM(1), %VMM(1), %k0{%k1}
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KMOV %k0, %VRAX
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/* Compare [w]char for null, mask bit will be set for match. */
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRAX
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# else
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inc %VRAX
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# endif
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jz L(align_more)
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WCSCHR
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leaq (%rdi, %rax, CHAR_SIZE), %rax
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# else
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add %rdi, %rax
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# endif
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# ifndef USE_AS_STRCHRNUL
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cmp (%rax), %CHAR_REG
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jne L(zero)
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ret
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L(zero):
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xorl %eax, %eax
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# endif
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ret
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L(ret_vec_x3):
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subq $-VEC_SIZE, %rdi
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L(ret_vec_x2):
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subq $-VEC_SIZE, %rdi
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L(ret_vec_x1):
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WCSCHR
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leaq (%rdi, %rax, CHAR_SIZE), %rax
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# else
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add %rdi, %rax
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# endif
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# ifndef USE_AS_STRCHRNUL
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cmp (%rax), %CHAR_REG
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jne L(zero)
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# endif
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ret
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L(page_cross):
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mov %rdi, %rax
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movl %edi, %ecx
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# ifdef USE_AS_WCSCHR
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/* Calculate number of compare result bits to be skipped for
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wide string alignment adjustment. */
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andl $(VEC_SIZE - 1), %ecx
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sarl $2, %ecx
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# endif
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/* ecx contains number of w[char] to be skipped as a result
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of address alignment. */
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andq $-VEC_SIZE, %rax
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VMOVA (%rax), %VMM(1)
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VPCMPNE %VMM(1), %VMM(0), %k1
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VPTEST %VMM(1), %VMM(1), %k0{%k1}
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KMOV %k0, %VRAX
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRAX
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# else
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inc %VRAX
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# endif
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/* Ignore number of character for alignment adjustment. */
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shr %cl, %VRAX
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jz L(align_more)
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bsf %VRAX, %VRAX
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# ifdef USE_AS_WCSCHR
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leaq (%rdi, %rax, CHAR_SIZE), %rax
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# else
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addq %rdi, %rax
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# endif
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# ifndef USE_AS_STRCHRNUL
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cmp (%rax), %CHAR_REG
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jne L(zero)
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# endif
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ret
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L(align_more):
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/* Align rax to VEC_SIZE. */
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andq $-VEC_SIZE, %rdi
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/* Loop unroll 4 times for 4 vector loop. */
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VMOVA VEC_SIZE(%rdi), %VMM(1)
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VPCMPNE %VMM(1), %VMM(0), %k1
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VPTEST %VMM(1), %VMM(1), %k0{%k1}
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/* Increment rdi by vector size for further comparison and
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return. */
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subq $-VEC_SIZE, %rdi
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KMOV %k0, %VRAX
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRAX
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# else
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inc %VRAX
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# endif
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jnz L(ret_vec_x1)
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VMOVA VEC_SIZE(%rdi), %VMM(1)
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VPCMPNE %VMM(1), %VMM(0), %k1
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VPTEST %VMM(1), %VMM(1), %k0{%k1}
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KMOV %k0, %VRAX
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRAX
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# else
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inc %VRAX
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# endif
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jnz L(ret_vec_x2)
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VMOVA (VEC_SIZE * 2)(%rdi), %VMM(1)
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VPCMPNE %VMM(1), %VMM(0), %k1
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VPTEST %VMM(1), %VMM(1), %k0{%k1}
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KMOV %k0, %VRAX
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRAX
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# else
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inc %VRAX
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# endif
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jnz L(ret_vec_x3)
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VMOVA (VEC_SIZE * 3)(%rdi), %VMM(1)
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VPCMPNE %VMM(1), %VMM(0), %k1
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VPTEST %VMM(1), %VMM(1), %k0{%k1}
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KMOV %k0, %VRDX
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRDX
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# else
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inc %VRDX
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# endif
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jnz L(ret_vec_x4)
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/* Align address to VEC_SIZE * 4 for loop. */
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andq $-(VEC_SIZE * 4), %rdi
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L(loop):
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/* VPMINU and VPCMP combination provide better performance as
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compared to alternative combinations. */
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VMOVA (VEC_SIZE * 4)(%rdi), %VMM(1)
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VMOVA (VEC_SIZE * 5)(%rdi), %VMM(2)
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VMOVA (VEC_SIZE * 6)(%rdi), %VMM(3)
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VMOVA (VEC_SIZE * 7)(%rdi), %VMM(4)
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VPCMPNE %VMM(1), %VMM(0), %k1
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VPCMPNE %VMM(2), %VMM(0), %k2
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VPMINU %VMM(2), %VMM(1), %VMM(2)
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VPCMPNE %VMM(3), %VMM(0), %k3{%k1}
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VPCMPNE %VMM(4), %VMM(0), %k4{%k2}
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VPMINU %VMM(4), %VMM(3), %VMM(4)
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VPMINU %VMM(2), %VMM(4), %VMM(4){%k3}{z}
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VPTEST %VMM(4), %VMM(4), %k5{%k4}
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KMOV %k5, %VRDX
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subq $-(VEC_SIZE * 4), %rdi
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRDX
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# else
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inc %VRDX
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# endif
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jz L(loop)
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VPTEST %VMM(1), %VMM(1), %k0{%k1}
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KMOV %k0, %VRAX
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRAX
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# else
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inc %VRAX
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# endif
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jnz L(ret_vec_x1)
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VPTEST %VMM(2), %VMM(2), %k0{%k2}
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KMOV %k0, %VRAX
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/* At this point, if k1 is non zero, null char must be in the
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second vector. */
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRAX
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# else
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inc %VRAX
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# endif
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jnz L(ret_vec_x2)
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VPTEST %VMM(3), %VMM(3), %k0{%k3}
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KMOV %k0, %VRAX
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# ifdef USE_AS_WCSCHR
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sub $VEC_MATCH_MASK, %VRAX
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# else
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inc %VRAX
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# endif
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jnz L(ret_vec_x3)
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/* At this point null [w]char must be in the fourth vector so no
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need to check. */
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L(ret_vec_x4):
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bsf %VRDX, %VRDX
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leaq (VEC_SIZE * 3)(%rdi, %rdx, CHAR_SIZE), %rax
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# ifndef USE_AS_STRCHRNUL
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cmp (%rax), %CHAR_REG
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jne L(zero_2)
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# endif
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ret
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# ifndef USE_AS_STRCHRNUL
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L(zero_2):
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xor %eax, %eax
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ret
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# endif
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END (STRCHR)
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#endif
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8
sysdeps/x86_64/multiarch/strchr-evex512.S
Normal file
8
sysdeps/x86_64/multiarch/strchr-evex512.S
Normal file
@ -0,0 +1,8 @@
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# ifndef STRCHR
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# define STRCHR __strchr_evex512
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# endif
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#include "x86-evex512-vecs.h"
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#include "reg-macros.h"
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#include "strchr-evex-base.S"
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8
sysdeps/x86_64/multiarch/strchrnul-evex512.S
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8
sysdeps/x86_64/multiarch/strchrnul-evex512.S
Normal file
@ -0,0 +1,8 @@
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#ifndef STRCHRNUL
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# define STRCHRNUL __strchrnul_evex512
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#endif
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#define STRCHR STRCHRNUL
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#define USE_AS_STRCHRNUL 1
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#include "strchr-evex512.S"
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9
sysdeps/x86_64/multiarch/wcschr-evex512.S
Normal file
9
sysdeps/x86_64/multiarch/wcschr-evex512.S
Normal file
@ -0,0 +1,9 @@
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#ifndef WCSCHR
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# define WCSCHR __wcschr_evex512
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#endif
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#define STRCHR WCSCHR
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#define USE_AS_WCSCHR 1
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#define USE_WIDE_CHAR 1
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#include "strchr-evex512.S"
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