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x86: Black list more Intel CPUs for TSX [BZ #27398]
Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in:
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
This fixes BZ #27398.
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
(cherry picked from commit 1e000d3d33
)
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parent
5b99f172b8
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@ -397,11 +397,42 @@ init_cpu_features (struct cpu_features *cpu_features)
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break;
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}
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/* Disable TSX on some Haswell processors to avoid TSX on kernels that
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weren't updated with the latest microcode package (which disables
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broken feature by default). */
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/* Disable TSX on some processors to avoid TSX on kernels that
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weren't updated with the latest microcode package (which
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disables broken feature by default). */
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switch (model)
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{
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case 0x55:
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if (stepping <= 5)
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goto disable_tsx;
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break;
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case 0x8e:
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/* NB: Although the errata documents that for model == 0x8e,
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only 0xb stepping or lower are impacted, the intention of
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the errata was to disable TSX on all client processors on
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all steppings. Include 0xc stepping which is an Intel
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Core i7-8665U, a client mobile processor. */
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case 0x9e:
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if (stepping > 0xc)
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break;
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/* Fall through. */
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case 0x4e:
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case 0x5e:
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{
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/* Disable Intel TSX and enable RTM_ALWAYS_ABORT for
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processors listed in:
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https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
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*/
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disable_tsx:
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cpu_features->cpuid[index_cpu_HLE].reg_HLE
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&= ~bit_cpu_HLE;
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cpu_features->cpuid[index_cpu_RTM].reg_RTM
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&= ~bit_cpu_RTM;
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cpu_features->cpuid[index_cpu_RTM_ALWAYS_ABORT].reg_RTM_ALWAYS_ABORT
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|= bit_cpu_RTM_ALWAYS_ABORT;
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}
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break;
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case 0x3f:
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/* Xeon E7 v3 with stepping >= 4 has working TSX. */
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if (stepping >= 4)
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