AuroraMiddleware/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2024-12-12 14:20:13 +00:00
Code Issues Packages Projects Releases Wiki Activity

x86: Black list more Intel CPUs for TSX [BZ #27398]

Browse Source 
Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in:

https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

This fixes BZ #27398.

Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
(cherry picked from commit 1e000d3d33)
This commit is contained in:
H.J. Lu 2022-01-14 14:48:01 -08:00
parent 5b99f172b8
commit 5db3239baf
1 changed files with 34 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
sysdeps/x86/cpu-features.c
View File

@ -397,11 +397,42 @@ init_cpu_features (struct cpu_features *cpu_features)
break;
}
/* Disable TSX on some Haswell processors to avoid TSX on kernels that
weren't updated with the latest microcode package (which disables
broken feature by default). */
/* Disable TSX on some processors to avoid TSX on kernels that
weren't updated with the latest microcode package (which
disables broken feature by default). */
switch (model)
{
case 0x55:
if (stepping <= 5)
goto disable_tsx;
break;
case 0x8e:
/* NB: Although the errata documents that for model == 0x8e,
only 0xb stepping or lower are impacted, the intention of
the errata was to disable TSX on all client processors on
all steppings. Include 0xc stepping which is an Intel
Core i7-8665U, a client mobile processor. */
case 0x9e:
if (stepping > 0xc)
break;
/* Fall through. */
case 0x4e:
case 0x5e:
{
/* Disable Intel TSX and enable RTM_ALWAYS_ABORT for
processors listed in:
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
*/
disable_tsx:
cpu_features->cpuid[index_cpu_HLE].reg_HLE
&= ~bit_cpu_HLE;
cpu_features->cpuid[index_cpu_RTM].reg_RTM
&= ~bit_cpu_RTM;
cpu_features->cpuid[index_cpu_RTM_ALWAYS_ABORT].reg_RTM_ALWAYS_ABORT
|= bit_cpu_RTM_ALWAYS_ABORT;
}
break;
case 0x3f:
/* Xeon E7 v3 with stepping >= 4 has working TSX. */
if (stepping >= 4)