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Merge branch 'master' of ssh://sourceware.org/git/glibc

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Ulrich Drepper 2011-08-20 15:17:30 -04:00
commit 5dc4290c5b
3 changed files with 26 additions and 7 deletions
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5
nptl/ChangeLog
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2011-08-14 Roland McGrath <roland@hack.frob.com>
* sysdeps/i386/pthreaddef.h (TCB_ALIGNMENT): Set to 64, optimal on Atom.
* sysdeps/x86_64/pthreaddef.h (TCB_ALIGNMENT): Likewise.
2011-08-08 Andreas Schwab <schwab@redhat.com> 2011-08-08 Andreas Schwab <schwab@redhat.com>
* sysdeps/unix/sysv/linux/x86_64/cancellation.S: Maintain aligned * sysdeps/unix/sysv/linux/x86_64/cancellation.S: Maintain aligned

12
nptl/sysdeps/i386/pthreaddef.h
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/* Copyright (C) 2002, 2003 Free Software Foundation, Inc. /* Copyright (C) 2002,2003,2011 Free Software Foundation, Inc.
This file is part of the GNU C Library. This file is part of the GNU C Library.
Contributed by Ulrich Drepper <drepper@redhat.com>, 2002. Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
@ -27,8 +27,14 @@
/* Minimal stack size after allocating thread descriptor and guard size. */ /* Minimal stack size after allocating thread descriptor and guard size. */
#define MINIMAL_REST_STACK 2048 #define MINIMAL_REST_STACK 2048
/* Alignment requirement for TCB. */ /* Alignment requirement for TCB.
#define TCB_ALIGNMENT 16
Some processors such as Intel Atom pay a big penalty on every
access using a segment override if that segment's base is not
aligned to the size of a cache line. (See Intel 64 and IA-32
Architectures Optimization Reference Manual, section 13.3.3.3,
"Segment Base".) On such machines, a cache line is 64 bytes. */
#define TCB_ALIGNMENT 64
/* Location of current stack frame. */ /* Location of current stack frame. */

16
nptl/sysdeps/x86_64/pthreaddef.h
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/* Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc. /* Copyright (C) 2002,2003,2007,2011 Free Software Foundation, Inc.
This file is part of the GNU C Library. This file is part of the GNU C Library.
Contributed by Ulrich Drepper <drepper@redhat.com>, 2002. Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
@ -27,9 +27,17 @@
/* Minimal stack size after allocating thread descriptor and guard size. */ /* Minimal stack size after allocating thread descriptor and guard size. */
#define MINIMAL_REST_STACK 2048 #define MINIMAL_REST_STACK 2048
/* Alignment requirement for TCB. Need to store post-AVX vector registers /* Alignment requirement for TCB.
in the TCB and we want the storage to be aligned at 32-byte. */
#define TCB_ALIGNMENT 32 We need to store post-AVX vector registers in the TCB and we want the
storage to be aligned to at least 32 bytes.
Some processors such as Intel Atom pay a big penalty on every
access using a segment override if that segment's base is not
aligned to the size of a cache line. (See Intel 64 and IA-32
Architectures Optimization Reference Manual, section 13.3.3.3,
"Segment Base".) On such machines, a cache line is 64 bytes. */
#define TCB_ALIGNMENT 64
/* Location of current stack frame. The frame pointer is not usable. */ /* Location of current stack frame. The frame pointer is not usable. */