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Skip SSE4.2 versions on Intel Silvermont
SSE2/SSSE3 versions are faster than SSE4.2 versions on Intel Silvermont.
This commit is contained in:
Liubov Dmitrieva
H.J. Lu
parent
89cd956937
commit
6308fd9a46
14
ChangeLog
14
ChangeLog
@ -1,3 +1,17 @@
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2013-06-28 Liubov Dmitrieva <liubov.dmitrieva@intel.com>
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* sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): Set
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bit_Slow_SSE4_2 and bit_Prefer_PMINUB_for_stringop for Intel
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Silvermont.
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* sysdeps/x86_64/multiarch/init-arch.h (bit_Slow_SSE4_2): New
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macro.
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(index_Slow_SSE4_2): Likewise.
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(index_Prefer_PMINUB_for_stringop): Likewise.
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* sysdeps/x86_64/multiarch/strchr.S: Skip SSE4.2 version if
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bit_Slow_SSE4_2 is set.
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* sysdeps/x86_64/multiarch/strcmp.S: Likewise.
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* sysdeps/x86_64/multiarch/strrchr.S: Likewise.
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2013-06-28 Ryan S. Arnold <rsa@linux.vnet.ibm.com>
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* sysdeps/powerpc/Makefile: Add comment about generating an offset to
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@ -81,8 +81,16 @@ __init_cpu_features (void)
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case 0x37:
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/* Unaligned load versions are faster than SSSE3
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on Silvermont. */
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#if index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop
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# error index_Fast_Unaligned_Load != index_Prefer_PMINUB_for_stringop
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#endif
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#if index_Fast_Unaligned_Load != index_Slow_SSE4_2
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# error index_Fast_Unaligned_Load != index_Slow_SSE4_2
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#endif
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__cpu_features.feature[index_Fast_Unaligned_Load]
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|= bit_Fast_Unaligned_Load;
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|= (bit_Fast_Unaligned_Load
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| bit_Prefer_PMINUB_for_stringop
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| bit_Slow_SSE4_2);
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break;
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default:
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@ -23,6 +23,7 @@
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#define bit_AVX_Usable (1 << 6)
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#define bit_FMA_Usable (1 << 7)
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#define bit_FMA4_Usable (1 << 8)
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#define bit_Slow_SSE4_2 (1 << 9)
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/* CPUID Feature flags. */
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@ -62,6 +63,7 @@
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# define index_AVX_Usable FEATURE_INDEX_1*FEATURE_SIZE
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# define index_FMA_Usable FEATURE_INDEX_1*FEATURE_SIZE
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# define index_FMA4_Usable FEATURE_INDEX_1*FEATURE_SIZE
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# define index_Slow_SSE4_2 FEATURE_INDEX_1*FEATURE_SIZE
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#else /* __ASSEMBLER__ */
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@ -156,9 +158,11 @@ extern const struct cpu_features *__get_cpu_features (void)
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# define index_Fast_Copy_Backward FEATURE_INDEX_1
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# define index_Slow_BSF FEATURE_INDEX_1
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# define index_Fast_Unaligned_Load FEATURE_INDEX_1
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# define index_Prefer_PMINUB_for_stringop FEATURE_INDEX_1
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# define index_AVX_Usable FEATURE_INDEX_1
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# define index_FMA_Usable FEATURE_INDEX_1
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# define index_FMA4_Usable FEATURE_INDEX_1
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# define index_Slow_SSE4_2 FEATURE_INDEX_1
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# define HAS_ARCH_FEATURE(name) \
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((__get_cpu_features ()->feature[index_##name] & (bit_##name)) != 0)
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@ -29,6 +29,8 @@ ENTRY(strchr)
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jne 1f
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call __init_cpu_features
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1: leaq __strchr_sse2(%rip), %rax
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testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
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jnz 2f
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testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
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jz 2f
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leaq __strchr_sse42(%rip), %rax
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@ -88,14 +88,16 @@ ENTRY(STRCMP)
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jne 1f
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call __init_cpu_features
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1:
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testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
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jnz 2f
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leaq STRCMP_SSE42(%rip), %rax
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testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
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jnz 2f
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leaq STRCMP_SSSE3(%rip), %rax
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jnz 3f
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2: leaq STRCMP_SSSE3(%rip), %rax
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testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip)
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jnz 2f
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jnz 3f
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leaq STRCMP_SSE2(%rip), %rax
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2: ret
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3: ret
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END(STRCMP)
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# ifdef USE_AS_STRCASECMP_L
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@ -109,16 +111,18 @@ ENTRY(__strcasecmp)
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# ifdef HAVE_AVX_SUPPORT
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leaq __strcasecmp_avx(%rip), %rax
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testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
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jnz 2f
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jnz 3f
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# endif
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testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
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jnz 2f
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leaq __strcasecmp_sse42(%rip), %rax
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testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
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jnz 2f
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leaq __strcasecmp_ssse3(%rip), %rax
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jnz 3f
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2: leaq __strcasecmp_ssse3(%rip), %rax
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testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip)
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jnz 2f
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jnz 3f
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leaq __strcasecmp_sse2(%rip), %rax
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2: ret
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3: ret
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END(__strcasecmp)
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weak_alias (__strcasecmp, strcasecmp)
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# endif
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@ -133,16 +137,18 @@ ENTRY(__strncasecmp)
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# ifdef HAVE_AVX_SUPPORT
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leaq __strncasecmp_avx(%rip), %rax
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testl $bit_AVX_Usable, __cpu_features+FEATURE_OFFSET+index_AVX_Usable(%rip)
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jnz 2f
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jnz 3f
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# endif
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testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
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jnz 2f
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leaq __strncasecmp_sse42(%rip), %rax
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testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
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jnz 2f
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leaq __strncasecmp_ssse3(%rip), %rax
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jnz 3f
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2: leaq __strncasecmp_ssse3(%rip), %rax
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testl $bit_SSSE3, __cpu_features+CPUID_OFFSET+index_SSSE3(%rip)
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jnz 2f
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jnz 3f
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leaq __strncasecmp_sse2(%rip), %rax
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2: ret
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3: ret
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END(__strncasecmp)
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weak_alias (__strncasecmp, strncasecmp)
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# endif
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@ -32,6 +32,8 @@ ENTRY(strrchr)
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jne 1f
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call __init_cpu_features
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1: leaq __strrchr_sse2(%rip), %rax
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testl $bit_Slow_SSE4_2, __cpu_features+CPUID_OFFSET+index_Slow_SSE4_2(%rip)
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jnz 2f
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testl $bit_SSE4_2, __cpu_features+CPUID_OFFSET+index_SSE4_2(%rip)
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jz 2f
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leaq __strrchr_sse42(%rip), %rax
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