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* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Pass correct value
as second parameter to handle_intel.
This commit is contained in:
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commit
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@ -1,5 +1,8 @@
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2007-05-21 Ulrich Drepper <drepper@redhat.com>
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* sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Pass correct value
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as second parameter to handle_intel.
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* nscd/aicache.c (addhstaiX): If reported TTL is zero don't cache
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the entry.
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@ -51,6 +54,7 @@
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Define for kernel >= 2.6.22.
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2007-05-18 Ulrich Drepper <drepper@redhat.com>
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* elf/dl-close.c (_dl_close_worker): When removing object from
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global scope, wait for all lookups to finish afterwards.
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* elf/dl-open.c (add_to_global): When global scope array must
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@ -1,3 +1,15 @@
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2007-05-21 Ulrich Drepper <drepper@redhat.com>
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* sysdeps/pthread/pthread-functions.h (struct pthread_functions):
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Remove ptr_wait_lookup_done again.
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* init.c (pthread_functions): Don't add .ptr_wait_lookup_done here.
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(__pthread_initialize_minimal_internal): Initialize
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_dl_wait_lookup_done pointer in _rtld_global directly.
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* sysdeps/unix/sysv/linux/libc_pthread_init.c (__libc_pthread_init):
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Remove code to code _dl_wait_lookup_done.
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* sysdeps/x86_64/tls.h (THREAD_GSCOPE_WAIT): The pointer is not
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encrypted for now.
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2007-05-21 Jakub Jelinek <jakub@redhat.com>
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* tst-robust9.c (do_test): Don't fail if ENABLE_PI and
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@ -97,7 +97,6 @@ struct pthread_functions
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void (*ptr__nptl_deallocate_tsd) (void);
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int (*ptr__nptl_setxid) (struct xid_command *);
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void (*ptr_freeres) (void);
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void (*ptr_wait_lookup_done) (void);
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};
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/* Variable in libc.so. */
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@ -71,12 +71,6 @@ __libc_pthread_init (ptr, reclaim, functions)
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dest->parr[cnt] = p;
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}
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__libc_pthread_functions_init = 1;
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# ifdef RTLD_NOT_MANGLED
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GL(dl_wait_lookup_done) = functions->ptr_wait_lookup_done;
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# else
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GL(dl_wait_lookup_done) = __libc_pthread_functions.ptr_wait_lookup_done;
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# endif
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#endif
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#ifndef TLS_MULTIPLE_THREADS_IN_TCB
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@ -357,10 +357,7 @@ typedef struct
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#define THREAD_GSCOPE_SET_FLAG() \
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THREAD_SETMEM (THREAD_SELF, header.gscope_flag, THREAD_GSCOPE_FLAG_USED)
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#define THREAD_GSCOPE_WAIT() \
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do { void (*ptr) (void) = GL(dl_wait_lookup_done); \
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PTR_DEMANGLE (ptr); \
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ptr (); \
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} while (0)
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GL(dl_wait_lookup_done) ()
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#endif /* __ASSEMBLER__ */
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@ -1,6 +1,4 @@
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/*
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x86_64 cache info.
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/* x86_64 cache info.
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Copyright (C) 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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@ -202,7 +200,7 @@ handle_intel (int name, unsigned int maxidx)
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long int result = 0;
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bool no_level_2_or_3 = false;
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bool has_level_2 = false;
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while (cnt++ < max)
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{
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unsigned int eax;
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@ -349,7 +347,8 @@ __cache_sysconf (int name)
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/* Half the core cache size for use in memory and string routines, typically
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L1 size. */
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long int __x86_64_core_cache_size_half attribute_hidden = 32 * 1024 / 2;
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/* Shared cache size for use in memory and string routines, typically L2 or L3 size. */
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/* Shared cache size for use in memory and string routines, typically
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L2 or L3 size. */
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long int __x86_64_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
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/* PREFETCHW support flag for use in memory and string routines. */
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int __x86_64_prefetchw attribute_hidden;
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@ -378,24 +377,25 @@ init_cacheinfo (void)
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/* This spells out "GenuineIntel". */
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
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{
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core = handle_intel (_SC_LEVEL1_DCACHE_SIZE, eax);
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core = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
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/* Try L3 first. */
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level = 3;
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shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, eax);
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shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
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if (shared <= 0)
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{
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/* Try L2 otherwise. */
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level = 2;
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shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, eax);
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shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
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}
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/* Figure out the number of logical threads that share the highest cache level. */
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/* Figure out the number of logical threads that share the
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highest cache level. */
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if (max_cpuid >= 4)
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{
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int i = 0;
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/* Query until desired cache level is enumerated. */
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do
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{
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@ -404,7 +404,7 @@ init_cacheinfo (void)
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: "0" (4), "2" (i++));
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}
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while (((eax >> 5) & 0x7) != level);
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threads = ((eax >> 14) & 0x3ff) + 1;
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}
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else
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@ -413,11 +413,12 @@ init_cacheinfo (void)
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asm volatile ("cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (1));
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threads = (ebx >> 16) & 0xff;
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}
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/* Cap usage of highest cache level to the number of supported threads. */
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/* Cap usage of highest cache level to the number of supported
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threads. */
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if (shared > 0 && threads > 0)
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shared /= threads;
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}
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@ -426,7 +427,7 @@ init_cacheinfo (void)
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{
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core = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
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shared = handle_amd (_SC_LEVEL2_CACHE_SIZE);
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asm volatile ("cpuid"
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: "=a" (max_cpuid_ex), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (0x80000000));
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