AuroraMiddleware/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2024-09-20 08:30:00 +00:00
Code Issues Packages Projects Releases Wiki Activity

powerpc: Revert to default atomic ops in elision code

Browse Source 
Power ISA 2.07B section B.5.5 relaxed the barrier requirement around a
TLE enabled lock.  It is now identical to a traditional lock.

2015-08-26  Paul E. Murphy  <murphyp@linux.vnet.ibm.com>

	* sysdeps/unix/sysv/linux/powerpc/elision-lock.c
	(__arch_compare_and_exchange_val_32_acq): Remove and use common
	definition.  ISA 2.07B no longer requires full sync.
This commit is contained in:
Paul E. Murphy 2015-08-13 16:21:05 -05:00 committed by Tulio Magno Quites Machado Filho
parent a2ab38c9b8
commit 6eb901de9b
2 changed files with 6 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ChangeLog
View File

@ -1,3 +1,9 @@
2015-08-26 Paul E. Murphy <murphyp@linux.vnet.ibm.com>
* sysdeps/unix/sysv/linux/powerpc/elision-lock.c
(__arch_compare_and_exchange_val_32_acq): Remove and use common
definition. ISA 2.07B no longer requires full sync.
2015-08-26 Mike Frysinger <vapier@gentoo.org>
[BZ #18863]

21
sysdeps/unix/sysv/linux/powerpc/elision-lock.c
View File

@ -23,27 +23,6 @@
#include <elision-conf.h>
#include "htm.h"
/* PowerISA 2.0.7 Section B.5.5 defines isync to be insufficient as a
barrier in acquire mechanism for HTM operations, a strong 'sync' is
required. */
#undef __arch_compare_and_exchange_val_32_acq
#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \
__typeof (mem) __memp = (mem); \
__asm __volatile ( \
"1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n" \
" cmpw %0,%2\n" \
" bne 2f\n" \
" stwcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: sync" \
: "=&r" (__tmp) \
: "b" (__memp), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp; \
})
#if !defined(LLL_LOCK) && !defined(EXTRAARG)
/* Make sure the configuration code is always linked in for static
libraries. */