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* sysdeps/powerpc/dl-machine.c: Many minor formatting changes. (OPCODE_LWZU): New macro. (OPCODE_ADDIS_HI): New macro. (OPCODE_LIS_HI): New macro. (__elf_machine_runtime_setup): Change PLT code-generation scheme for thread safety even with very large PLTs, better efficiency, and to fix a cache-flushing bug. Also support the Motorola 8xx processors which have a different cache line size than all the others. (__elf_machine_fixup_plt): Likewise. (__process_machine_rela): Don't use elf_machine_fixup_plt.
1999-12-30 Geoffrey Keating <geoffk@cygnus.com> * sysdeps/powerpc/dl-machine.c: Many minor formatting changes. (OPCODE_LWZU): New macro. (OPCODE_ADDIS_HI): New macro. (OPCODE_LIS_HI): New macro. (__elf_machine_runtime_setup): Change PLT code-generation scheme for thread safety even with very large PLTs, better efficiency, and to fix a cache-flushing bug. Also support the Motorola 8xx processors which have a different cache line size than all the others. (__elf_machine_fixup_plt): Likewise. (__process_machine_rela): Don't use elf_machine_fixup_plt.
This commit is contained in:
Geoff Keating
parent
83d660c76f
commit
7137f4248d
14
ChangeLog
14
ChangeLog
@ -1,3 +1,17 @@
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1999-12-30 Geoffrey Keating <geoffk@cygnus.com>
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* sysdeps/powerpc/dl-machine.c: Many minor formatting changes.
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(OPCODE_LWZU): New macro.
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(OPCODE_ADDIS_HI): New macro.
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(OPCODE_LIS_HI): New macro.
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(__elf_machine_runtime_setup): Change PLT code-generation scheme
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for thread safety even with very large PLTs, better efficiency,
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and to fix a cache-flushing bug. Also support the Motorola
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8xx processors which have a different cache line size than all
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the others.
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(__elf_machine_fixup_plt): Likewise.
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(__process_machine_rela): Don't use elf_machine_fixup_plt.
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1999-12-30 Ulrich Drepper <drepper@cygnus.com>
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* wcsmbs/wcscoll.c: Use multibyte character version.
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@ -33,17 +33,19 @@
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#endif
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/* stuff for the PLT */
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/* Stuff for the PLT. */
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#define PLT_INITIAL_ENTRY_WORDS 18
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#define PLT_LONGBRANCH_ENTRY_WORDS 10
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#define PLT_LONGBRANCH_ENTRY_WORDS 0
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#define PLT_TRAMPOLINE_ENTRY_WORDS 6
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#define PLT_DOUBLE_SIZE (1<<13)
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#define PLT_ENTRY_START_WORDS(entry_number) \
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(PLT_INITIAL_ENTRY_WORDS + (entry_number)*2 + \
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((entry_number) > PLT_DOUBLE_SIZE ? \
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((entry_number) - PLT_DOUBLE_SIZE)*2 : \
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0))
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(PLT_INITIAL_ENTRY_WORDS + (entry_number)*2 \
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+ ((entry_number) > PLT_DOUBLE_SIZE \
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? ((entry_number) - PLT_DOUBLE_SIZE)*2 \
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: 0))
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#define PLT_DATA_START_WORDS(num_entries) PLT_ENTRY_START_WORDS(num_entries)
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/* Macros to build PowerPC opcode words. */
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#define OPCODE_ADDI(rd,ra,simm) \
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(0x38000000 | (rd) << 21 | (ra) << 16 | ((simm) & 0xffff))
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#define OPCODE_ADDIS(rd,ra,simm) \
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@ -55,11 +57,16 @@
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#define OPCODE_BCTR() 0x4e800420
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#define OPCODE_LWZ(rd,d,ra) \
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(0x80000000 | (rd) << 21 | (ra) << 16 | ((d) & 0xffff))
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#define OPCODE_LWZU(rd,d,ra) \
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(0x84000000 | (rd) << 21 | (ra) << 16 | ((d) & 0xffff))
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#define OPCODE_MTCTR(rd) (0x7C0903A6 | (rd) << 21)
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#define OPCODE_RLWINM(ra,rs,sh,mb,me) \
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(0x54000000 | (rs) << 21 | (ra) << 16 | (sh) << 11 | (mb) << 6 | (me) << 1)
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#define OPCODE_LI(rd,simm) OPCODE_ADDI(rd,0,simm)
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#define OPCODE_ADDIS_HI(rd,ra,value) \
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OPCODE_ADDIS(rd,ra,((value) + 0x8000) >> 16)
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#define OPCODE_LIS_HI(rd,value) OPCODE_ADDIS_HI(rd,0,value)
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#define OPCODE_SLWI(ra,rs,sh) OPCODE_RLWINM(ra,rs,sh,0,31-sh)
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@ -136,131 +143,172 @@ __elf_preferred_address(struct link_map *loader, size_t maplength,
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Also install a small trampoline to be used by entries that have
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been relocated to an address too far away for a single branch. */
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/* A PLT entry does one of three things:
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(i) Jumps to the actual routine. Such entries are set up above, in
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elf_machine_rela.
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/* There are many kinds of PLT entries:
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(ii) Jumps to the actual routine via glue at the start of the PLT.
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We do this by putting the address of the routine in space
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allocated at the end of the PLT, and when the PLT entry is
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called we load the offset of that word (from the start of the
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space) into r11, then call the glue, which loads the word and
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branches to that address. These entries are set up in
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elf_machine_rela, but the glue is set up here.
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(1) A direct jump to the actual routine, either a relative or
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absolute branch. These are set up in __elf_machine_fixup_plt.
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(iii) Loads the index of this PLT entry (we count the double-size
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entries as one entry for this purpose) into r11, then
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branches to code at the start of the PLT. This code then
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calls `fixup', in dl-runtime.c, via the glue in the macro
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ELF_MACHINE_RUNTIME_TRAMPOLINE, which resets the PLT entry to
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be one of the above two types. These entries are set up here. */
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(2) Short lazy entries. These cover the first 8192 slots in
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the PLT, and look like (where 'index' goes from 0 to 8191):
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li %r11, index*4
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b &plt[PLT_TRAMPOLINE_ENTRY_WORDS+1]
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(3) Short indirect jumps. These replace (2) when a direct jump
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wouldn't reach. They look the same except that the branch
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is 'b &plt[PLT_LONGBRANCH_ENTRY_WORDS]'.
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(4) Long lazy entries. These cover the slots when a short entry
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won't fit ('index*4' overflows its field), and look like:
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lis %r11, %hi(index*4 + &plt[PLT_DATA_START_WORDS])
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lwzu %r12, %r11, %lo(index*4 + &plt[PLT_DATA_START_WORDS])
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b &plt[PLT_TRAMPOLINE_ENTRY_WORDS]
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bctr
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(5) Long indirect jumps. These replace (4) when a direct jump
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wouldn't reach. They look like:
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lis %r11, %hi(index*4 + &plt[PLT_DATA_START_WORDS])
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lwz %r12, %r11, %lo(index*4 + &plt[PLT_DATA_START_WORDS])
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mtctr %r12
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bctr
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(6) Long direct jumps. These are used when thread-safety is not
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required. They look like:
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lis %r12, %hi(finaladdr)
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addi %r12, %r12, %lo(finaladdr)
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mtctr %r12
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bctr
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The lazy entries, (2) and (4), are set up here in
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__elf_machine_runtime_setup. (1), (3), and (5) are set up in
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__elf_machine_fixup_plt. (1), (3), and (6) can also be constructed
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in __process_machine_rela.
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The reason for the somewhat strange construction of the long
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entries, (4) and (5), is that we need to ensure thread-safety. For
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(1) and (3), this is obvious because only one instruction is
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changed and the PPC architecture guarantees that aligned stores are
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atomic. For (5), this is more tricky. When changing (4) to (5),
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the `b' instruction is first changed to to `mtctr'; this is safe
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and is why the `lwzu' instruction is not just a simple `addi'.
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Once this is done, and is visible to all processors, the `lwzu' can
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safely be changed to a `lwz'. */
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int
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__elf_machine_runtime_setup (struct link_map *map, int lazy, int profile)
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{
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if (map->l_info[DT_JMPREL])
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{
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Elf32_Word i;
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/* Fill in the PLT. Its initial contents are directed to a
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function earlier in the PLT which arranges for the dynamic
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linker to be called back. */
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Elf32_Word *plt = (Elf32_Word *) map->l_info[DT_PLTGOT]->d_un.d_val;
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Elf32_Word num_plt_entries = (map->l_info[DT_PLTRELSZ]->d_un.d_val
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/ sizeof (Elf32_Rela));
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Elf32_Word rel_offset_words = PLT_DATA_START_WORDS (num_plt_entries);
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Elf32_Word data_words = (Elf32_Word) (plt + rel_offset_words);
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Elf32_Word size_modified;
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extern void _dl_runtime_resolve (void);
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extern void _dl_prof_resolve (void);
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Elf32_Word dlrr;
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dlrr = (Elf32_Word)(char *)(profile
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? _dl_prof_resolve
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: _dl_runtime_resolve);
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if (profile && _dl_name_match_p (_dl_profile, map))
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/* This is the object we are looking for. Say that we really
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want profiling and the timers are started. */
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_dl_profile_map = map;
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if (lazy)
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for (i = 0; i < num_plt_entries; i++)
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{
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Elf32_Word offset = PLT_ENTRY_START_WORDS (i);
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if (i >= PLT_DOUBLE_SIZE)
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{
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plt[offset ] = OPCODE_LI (11, i * 4);
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plt[offset+1] = OPCODE_ADDIS (11, 11, (i * 4 + 0x8000) >> 16);
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plt[offset+2] = OPCODE_B (-(4 * (offset + 2)));
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}
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else
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{
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plt[offset ] = OPCODE_LI (11, i * 4);
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plt[offset+1] = OPCODE_B (-(4 * (offset + 1)));
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}
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}
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/* Multiply index of entry by 3 (in r11). */
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plt[0] = OPCODE_SLWI (12, 11, 1);
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plt[1] = OPCODE_ADD (11, 12, 11);
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if (dlrr <= 0x01fffffc || dlrr >= 0xfe000000)
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{
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/* Load address of link map in r12. */
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plt[2] = OPCODE_LI (12, (Elf32_Word) (char *) map);
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plt[3] = OPCODE_ADDIS (12, 12, (((Elf32_Word) (char *) map
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+ 0x8000) >> 16));
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/* Call _dl_runtime_resolve. */
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plt[4] = OPCODE_BA (dlrr);
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}
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else
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{
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/* Get address of _dl_runtime_resolve in CTR. */
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plt[2] = OPCODE_LI (12, dlrr);
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plt[3] = OPCODE_ADDIS (12, 12, (dlrr + 0x8000) >> 16);
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plt[4] = OPCODE_MTCTR (12);
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/* Load address of link map in r12. */
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plt[5] = OPCODE_LI (12, (Elf32_Word) (char *) map);
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plt[6] = OPCODE_ADDIS (12, 12, (((Elf32_Word) (char *) map
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+ 0x8000) >> 16));
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/* Call _dl_runtime_resolve. */
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plt[7] = OPCODE_BCTR ();
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}
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/* Convert the index in r11 into an actual address, and get the
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word at that address. */
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plt[PLT_LONGBRANCH_ENTRY_WORDS] =
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OPCODE_ADDIS (11, 11, (((Elf32_Word) (char*) (plt + rel_offset_words)
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+ 0x8000) >> 16));
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plt[PLT_LONGBRANCH_ENTRY_WORDS+1] =
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OPCODE_LWZ (11, (Elf32_Word) (char*) (plt + rel_offset_words), 11);
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plt[PLT_LONGBRANCH_ENTRY_WORDS] = OPCODE_ADDIS_HI (11, 11, data_words);
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plt[PLT_LONGBRANCH_ENTRY_WORDS + 1] = OPCODE_LWZ (11, data_words, 11);
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/* Call the procedure at that address. */
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plt[PLT_LONGBRANCH_ENTRY_WORDS + 2] = OPCODE_MTCTR (11);
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plt[PLT_LONGBRANCH_ENTRY_WORDS + 3] = OPCODE_BCTR ();
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if (lazy)
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{
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Elf32_Word *tramp = plt + PLT_TRAMPOLINE_ENTRY_WORDS;
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Elf32_Word dlrr = (Elf32_Word)(profile
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? _dl_prof_resolve
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: _dl_runtime_resolve);
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Elf32_Word offset;
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/* Now, we've modified code (quite a lot of code, possibly). We
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need to write the changes from the data cache to a
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second-level unified cache, then make sure that stale data in
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the instruction cache is removed. (In a multiprocessor
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system, the effect is more complex.) Most of the PLT shouldn't
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be in the instruction cache, but there may be a little overlap
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at the start and the end.
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if (profile && _dl_name_match_p (_dl_profile, map))
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/* This is the object we are looking for. Say that we really
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want profiling and the timers are started. */
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_dl_profile_map = map;
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Assumes the cache line size is at least 32 bytes, or at least
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that dcbst and icbi apply to 32-byte lines. At present, all
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PowerPC processors have line sizes of exactly 32 bytes. */
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/* For the long entries, subtract off data_words. */
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tramp[0] = OPCODE_ADDIS_HI (11, 11, -data_words);
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tramp[1] = OPCODE_ADDI (11, 11, -data_words);
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size_modified = lazy ? rel_offset_words : PLT_INITIAL_ENTRY_WORDS;
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for (i = 0; i < size_modified; i+= 8)
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/* Multiply index of entry by 3 (in r11). */
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tramp[2] = OPCODE_SLWI (12, 11, 1);
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tramp[3] = OPCODE_ADD (11, 12, 11);
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if (dlrr <= 0x01fffffc || dlrr >= 0xfe000000)
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{
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/* Load address of link map in r12. */
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tramp[4] = OPCODE_LI (12, (Elf32_Word) map);
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tramp[5] = OPCODE_ADDIS_HI (12, 12, (Elf32_Word) map);
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/* Call _dl_runtime_resolve. */
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tramp[6] = OPCODE_BA (dlrr);
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}
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else
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{
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/* Get address of _dl_runtime_resolve in CTR. */
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tramp[4] = OPCODE_LI (12, dlrr);
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tramp[5] = OPCODE_ADDIS_HI (12, 12, dlrr);
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tramp[6] = OPCODE_MTCTR (12);
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/* Load address of link map in r12. */
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tramp[7] = OPCODE_LI (12, (Elf32_Word) map);
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tramp[8] = OPCODE_ADDIS_HI (12, 12, (Elf32_Word) map);
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/* Call _dl_runtime_resolve. */
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tramp[9] = OPCODE_BCTR ();
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}
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/* Set up the lazy PLT entries. */
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offset = PLT_INITIAL_ENTRY_WORDS;
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i = 0;
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while (i < num_plt_entries && i < PLT_DOUBLE_SIZE)
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{
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plt[offset ] = OPCODE_LI (11, i * 4);
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plt[offset+1] = OPCODE_B ((PLT_TRAMPOLINE_ENTRY_WORDS + 2
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- (offset+1))
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* 4);
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i++;
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offset += 2;
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}
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while (i < num_plt_entries)
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{
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plt[offset ] = OPCODE_LIS_HI (11, i * 4 + data_words);
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plt[offset+1] = OPCODE_LWZU (12, i * 4 + data_words, 11);
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plt[offset+2] = OPCODE_B ((PLT_TRAMPOLINE_ENTRY_WORDS
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- (offset+2))
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* 4);
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plt[offset+3] = OPCODE_BCTR ();
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i++;
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offset += 4;
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}
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}
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/* Now, we've modified code. We need to write the changes from
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the data cache to a second-level unified cache, then make
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sure that stale data in the instruction cache is removed.
|
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(In a multiprocessor system, the effect is more complex.)
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Most of the PLT shouldn't be in the instruction cache, but
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there may be a little overlap at the start and the end.
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Assumes that dcbst and icbi apply to lines of 16 bytes or
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more. At present, all PowerPC processors have line sizes of
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16 or 32 bytes. */
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size_modified = lazy ? rel_offset_words : 6;
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for (i = 0; i < size_modified; i += 4)
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PPC_DCBST (plt + i);
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PPC_DCBST (plt + size_modified - 1);
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PPC_SYNC;
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PPC_ICBI (plt);
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PPC_ICBI (plt + size_modified-1);
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PPC_ICBI (plt + size_modified - 1);
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PPC_ISYNC;
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}
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@ -271,61 +319,45 @@ void
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__elf_machine_fixup_plt(struct link_map *map, const Elf32_Rela *reloc,
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Elf32_Addr *reloc_addr, Elf32_Addr finaladdr)
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{
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Elf32_Sword delta = finaladdr - (Elf32_Word) (char *) reloc_addr;
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Elf32_Sword delta = finaladdr - (Elf32_Word) reloc_addr;
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if (delta << 6 >> 6 == delta)
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*reloc_addr = OPCODE_B (delta);
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else if (finaladdr <= 0x01fffffc || finaladdr >= 0xfe000000)
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*reloc_addr = OPCODE_BA (finaladdr);
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else
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{
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Elf32_Word *plt;
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Elf32_Word index;
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Elf32_Word *plt, *data_words;
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Elf32_Word index, offset, num_plt_entries;
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num_plt_entries = (map->l_info[DT_PLTRELSZ]->d_un.d_val
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/ sizeof(Elf32_Rela));
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plt = (Elf32_Word *) map->l_info[DT_PLTGOT]->d_un.d_val;
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index = (reloc_addr - plt - PLT_INITIAL_ENTRY_WORDS)/2;
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if (index >= PLT_DOUBLE_SIZE)
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offset = reloc_addr - plt;
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index = (offset - PLT_INITIAL_ENTRY_WORDS)/2;
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data_words = plt + PLT_DATA_START_WORDS (num_plt_entries);
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reloc_addr += 1;
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if (index < PLT_DOUBLE_SIZE)
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{
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/* Slots greater than or equal to 2^13 have 4 words available
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instead of two. */
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/* FIXME: There are some possible race conditions in this code,
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when called from 'fixup'.
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1) Suppose that a lazy PLT entry is executing, a context switch
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between threads (or a signal) occurs, and the new thread or
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signal handler calls the same lazy PLT entry. Then the PLT entry
|
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would be changed while it's being run, which will cause a segfault
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(almost always).
|
||||
|
||||
2) Suppose the reverse: that a lazy PLT entry is being updated,
|
||||
a context switch occurs, and the new code calls the lazy PLT
|
||||
entry that is being updated. Then the half-fixed PLT entry will
|
||||
be executed, which will also almost always cause a segfault.
|
||||
|
||||
These problems don't happen with the 2-word entries, because
|
||||
only one of the two instructions are changed when a lazy entry
|
||||
is retargeted at the actual PLT entry; the li instruction stays
|
||||
the same (we have to update it anyway, because we might not be
|
||||
updating a lazy PLT entry). */
|
||||
|
||||
reloc_addr[0] = OPCODE_LI (11, finaladdr);
|
||||
reloc_addr[1] = OPCODE_ADDIS (11, 11, (finaladdr + 0x8000) >> 16);
|
||||
reloc_addr[2] = OPCODE_MTCTR (11);
|
||||
reloc_addr[3] = OPCODE_BCTR ();
|
||||
data_words[index] = finaladdr;
|
||||
PPC_SYNC;
|
||||
*reloc_addr = OPCODE_B ((PLT_LONGBRANCH_ENTRY_WORDS - (offset+1))
|
||||
* 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
Elf32_Word num_plt_entries;
|
||||
index -= (index - PLT_DOUBLE_SIZE)/2;
|
||||
|
||||
num_plt_entries = (map->l_info[DT_PLTRELSZ]->d_un.d_val
|
||||
/ sizeof(Elf32_Rela));
|
||||
data_words[index] = finaladdr;
|
||||
PPC_SYNC;
|
||||
|
||||
plt[index+PLT_DATA_START_WORDS (num_plt_entries)] = finaladdr;
|
||||
reloc_addr[0] = OPCODE_LI (11, index*4);
|
||||
reloc_addr[1] = OPCODE_B (-(4*(index*2
|
||||
+ 1
|
||||
- PLT_LONGBRANCH_ENTRY_WORDS
|
||||
+ PLT_INITIAL_ENTRY_WORDS)));
|
||||
reloc_addr += 1; /* This is the modified address. */
|
||||
reloc_addr[1] = OPCODE_MTCTR (12);
|
||||
MODIFIED_CODE_NOQUEUE (reloc_addr + 1);
|
||||
PPC_SYNC;
|
||||
|
||||
reloc_addr[0] = OPCODE_LWZ (12,
|
||||
(Elf32_Word) (data_words + index), 11);
|
||||
}
|
||||
}
|
||||
MODIFIED_CODE (reloc_addr);
|
||||
@ -394,7 +426,7 @@ __process_machine_rela (struct link_map *map,
|
||||
|
||||
case R_PPC_REL24:
|
||||
{
|
||||
Elf32_Sword delta = finaladdr - (Elf32_Word) (char *) reloc_addr;
|
||||
Elf32_Sword delta = finaladdr - (Elf32_Word) reloc_addr;
|
||||
if (delta << 6 >> 6 != delta)
|
||||
_dl_signal_error (0, map->l_name,
|
||||
"R_PPC_REL24 relocation out of range");
|
||||
@ -423,12 +455,52 @@ __process_machine_rela (struct link_map *map,
|
||||
return;
|
||||
|
||||
case R_PPC_REL32:
|
||||
*reloc_addr = finaladdr - (Elf32_Word) (char *) reloc_addr;
|
||||
*reloc_addr = finaladdr - (Elf32_Word) reloc_addr;
|
||||
return;
|
||||
|
||||
case R_PPC_JMP_SLOT:
|
||||
elf_machine_fixup_plt (map, reloc, reloc_addr, finaladdr);
|
||||
return;
|
||||
/* It used to be that elf_machine_fixup_plt was used here,
|
||||
but that doesn't work when ld.so relocates itself
|
||||
for the second time. On the bright side, there's
|
||||
no need to worry about thread-safety here. */
|
||||
{
|
||||
Elf32_Sword delta = finaladdr - (Elf32_Word) reloc_addr;
|
||||
if (delta << 6 >> 6 == delta)
|
||||
*reloc_addr = OPCODE_B (delta);
|
||||
else if (finaladdr <= 0x01fffffc || finaladdr >= 0xfe000000)
|
||||
*reloc_addr = OPCODE_BA (finaladdr);
|
||||
else
|
||||
{
|
||||
Elf32_Word *plt, *data_words;
|
||||
Elf32_Word index, offset, num_plt_entries;
|
||||
|
||||
plt = (Elf32_Word *) map->l_info[DT_PLTGOT]->d_un.d_val;
|
||||
offset = reloc_addr - plt;
|
||||
|
||||
if (offset < PLT_DOUBLE_SIZE*2 + PLT_INITIAL_ENTRY_WORDS)
|
||||
{
|
||||
index = (offset - PLT_INITIAL_ENTRY_WORDS)/2;
|
||||
num_plt_entries = (map->l_info[DT_PLTRELSZ]->d_un.d_val
|
||||
/ sizeof(Elf32_Rela));
|
||||
data_words = plt + PLT_DATA_START_WORDS (num_plt_entries);
|
||||
data_words[index] = finaladdr;
|
||||
reloc_addr[0] = OPCODE_LI (11, index * 4);
|
||||
reloc_addr[1] = OPCODE_B ((PLT_LONGBRANCH_ENTRY_WORDS
|
||||
- (offset+1))
|
||||
* 4);
|
||||
MODIFIED_CODE_NOQUEUE (reloc_addr + 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
reloc_addr[0] = OPCODE_LIS_HI (12, finaladdr);
|
||||
reloc_addr[1] = OPCODE_ADDI (12, 12, finaladdr);
|
||||
reloc_addr[2] = OPCODE_MTCTR (12);
|
||||
reloc_addr[3] = OPCODE_BCTR ();
|
||||
MODIFIED_CODE_NOQUEUE (reloc_addr + 3);
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
_dl_reloc_bad_type (map, rinfo, 0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user