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2003-05-12  Steven Munroe  <sjmunroe@us.ibm.com>

	* sysdeps/powerpc/bits/atomic.h
	(__arch_compare_and_exchange_bool_8_rel): Define.
	(__arch_compare_and_exchange_bool_16_rel): Define.
	(__ARCH_REL_INSTR): Define if not already defined.
	(__arch_atomic_exchange_and_add_32): Add "memory" to clobber list.
	(__arch_atomic_decrement_if_positive_32):
	Add "memory" to clobber list.
	(__arch_compare_and_exchange_val_32_acq): Remove release sync.
	(__arch_compare_and_exchange_val_32_rel): Define.
	(__arch_atomic_exchange_32): Remove.
	(__arch_atomic_exchange_32_acq): Define.
	(__arch_atomic_exchange_32_rel): Define.
	(atomic_compare_and_exchange_val_rel): Define.
	(atomic_exchange_acq): Use __arch_atomic_exchange_*_acq forms.
	(atomic_exchange_rel): Define.
	* sysdeps/powerpc/powerpc32/bits/atomic.h
	(__arch_compare_and_exchange_bool_32_acq): Remove release sync.
	(__arch_compare_and_exchange_bool_32_rel): Define.
	(__arch_compare_and_exchange_bool_64_rel): Define.
	(__arch_compare_and_exchange_val_64_rel): Define.
	(__arch_atomic_exchange_64): Remove.
	(__arch_atomic_exchange_64_acq): Define.
	(__arch_atomic_exchange_64_rel): Define.
	* sysdeps/powerpc/powerpc64/bits/atomic.h
	(__arch_compare_and_exchange_bool_32_rel): Define.
	(__arch_compare_and_exchange_bool_64_acq): Remove release sync.
	(__arch_compare_and_exchange_bool_64_rel): Define.
	(__arch_compare_and_exchange_val_64_acq): Remove release sync.
	(__arch_compare_and_exchange_val_64_rel): Define.
	(__arch_atomic_exchange_64): Remove.
	(__arch_atomic_exchange_64_acq): Define.
	(__arch_atomic_exchange_64_rel): Define.
	(__arch_atomic_exchange_and_add_64): Add "memory" to clobber list.
	(__arch_atomic_decrement_if_positive_64):
	Add "memory" to clobber list.
	[!UP](__ARCH_REL_INSTR): Define as lwsync.

	the space-padded-by-default conversion specifiers, %e, %k, %l.
This commit is contained in:
Ulrich Drepper 2003-05-13 21:14:28 +00:00
parent edf205d5ef
commit 7158eae4a8
7 changed files with 398 additions and 117 deletions
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41
ChangeLog
View File

@ -1,3 +1,42 @@
2003-05-12 Steven Munroe <sjmunroe@us.ibm.com>
* sysdeps/powerpc/bits/atomic.h
(__arch_compare_and_exchange_bool_8_rel): Define.
(__arch_compare_and_exchange_bool_16_rel): Define.
(__ARCH_REL_INSTR): Define if not already defined.
(__arch_atomic_exchange_and_add_32): Add "memory" to clobber list.
(__arch_atomic_decrement_if_positive_32):
Add "memory" to clobber list.
(__arch_compare_and_exchange_val_32_acq): Remove release sync.
(__arch_compare_and_exchange_val_32_rel): Define.
(__arch_atomic_exchange_32): Remove.
(__arch_atomic_exchange_32_acq): Define.
(__arch_atomic_exchange_32_rel): Define.
(atomic_compare_and_exchange_val_rel): Define.
(atomic_exchange_acq): Use __arch_atomic_exchange_*_acq forms.
(atomic_exchange_rel): Define.
* sysdeps/powerpc/powerpc32/bits/atomic.h
(__arch_compare_and_exchange_bool_32_acq): Remove release sync.
(__arch_compare_and_exchange_bool_32_rel): Define.
(__arch_compare_and_exchange_bool_64_rel): Define.
(__arch_compare_and_exchange_val_64_rel): Define.
(__arch_atomic_exchange_64): Remove.
(__arch_atomic_exchange_64_acq): Define.
(__arch_atomic_exchange_64_rel): Define.
* sysdeps/powerpc/powerpc64/bits/atomic.h
(__arch_compare_and_exchange_bool_32_rel): Define.
(__arch_compare_and_exchange_bool_64_acq): Remove release sync.
(__arch_compare_and_exchange_bool_64_rel): Define.
(__arch_compare_and_exchange_val_64_acq): Remove release sync.
(__arch_compare_and_exchange_val_64_rel): Define.
(__arch_atomic_exchange_64): Remove.
(__arch_atomic_exchange_64_acq): Define.
(__arch_atomic_exchange_64_rel): Define.
(__arch_atomic_exchange_and_add_64): Add "memory" to clobber list.
(__arch_atomic_decrement_if_positive_64):
Add "memory" to clobber list.
[!UP](__ARCH_REL_INSTR): Define as lwsync.
2003-05-11 Andreas Schwab <schwab@suse.de>
* io/Makefile ($(objpfx)ftwtest.out): Use absolute file names.
@ -9,7 +48,7 @@
2003-05-11 Jim Meyering <jim@meyering.net>
* time/strftime.c (my_strftime): Let the `-' (no-pad) flag affect
the space-padded-by-default conversion specifiers, %e, %k, %l.
the space-padded-by-default conversion specifiers, %e, %k, %l.
2003-05-11 Andreas Schwab <schwab@suse.de>

139
manual/texinfo.tex
View File

@ -3,7 +3,7 @@
% Load plain if necessary, i.e., if running under initex.
\expandafter\ifx\csname fmtname\endcsname\relax\input plain\fi
%
\def\texinfoversion{2003-02-03.16}
\def\texinfoversion{2003-05-04.08}
%
% Copyright (C) 1985, 1986, 1988, 1990, 1991, 1992, 1993, 1994, 1995,
% 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
@ -71,11 +71,11 @@
\message{Basics,}
\chardef\other=12
% We never want plain's outer \+ definition in Texinfo.
% We never want plain's \outer definition of \+ in Texinfo.
% For @tex, we can use \tabalign.
\let\+ = \relax
% Save some parts of plain tex whose names we will redefine.
% Save some plain tex macros whose names we will redefine.
\let\ptexb=\b
\let\ptexbullet=\bullet
\let\ptexc=\c
@ -88,10 +88,12 @@
\let\ptexgtr=>
\let\ptexhat=^
\let\ptexi=\i
\let\ptexindent=\indent
\let\ptexlbrace=\{
\let\ptexless=<
\let\ptexplus=+
\let\ptexrbrace=\}
\let\ptexslash=\/
\let\ptexstar=\*
\let\ptext=\t
@ -164,8 +166,9 @@
% Hyphenation fixes.
\hyphenation{ap-pen-dix}
\hyphenation{mini-buf-fer mini-buf-fers}
\hyphenation{eshell}
\hyphenation{mini-buf-fer mini-buf-fers}
\hyphenation{time-stamp}
\hyphenation{white-space}
% Margin to add to right of even pages, to left of odd pages.
@ -536,6 +539,9 @@
% @* forces a line break.
\def\*{\hfil\break\hbox{}\ignorespaces}
% @/ allows a line break.
\let\/=\allowbreak
% @. is an end-of-sentence period.
\def\.{.\spacefactor=3000 }
@ -721,8 +727,7 @@ where each line of input produces a line of output.}
\spacefactor=3000
}
% @page forces the start of a new page
% @page forces the start of a new page.
%
\def\page{\par\vfill\supereject}
@ -843,7 +848,8 @@ where each line of input produces a line of output.}
% @paragraphindent NCHARS
% We'll use ems for NCHARS, close enough.
% We cannot implement @paragraphindent asis, though.
% NCHARS can also be the word `asis' or `none'.
% We cannot feasibly implement @paragraphindent asis, though.
%
\def\asisword{asis} % no translation, these are keywords
\def\noneword{none}
@ -879,6 +885,53 @@ where each line of input produces a line of output.}
\fi
}
% @firstparagraphindent WORD
% If WORD is `none', then suppress indentation of the first paragraph
% after a section heading. If WORD is `insert', then do indentat such
% paragraphs.
%
% The paragraph indentation is suppressed or not by calling
% \suppressfirstparagraphindent, which the sectioning commands do. We
% switch the definition of this back and forth according to WORD. By
% default, we suppress indentation.
%
\def\suppressfirstparagraphindent{\dosuppressfirstparagraphindent}
\newdimen\currentparindent
%
\def\insertword{insert}
%
\def\firstparagraphindent{\parsearg\dofirstparagraphindent}
\def\dofirstparagraphindent#1{%
\def\temp{#1}%
\ifx\temp\noneword
\let\suppressfirstparagraphindent = \dosuppressfirstparagraphindent
\else\ifx\temp\insertword
\let\suppressfirstparagraphindent = \relax
\else
\errhelp = \EMsimple
\errmessage{Unknown @firstparagraphindent option `\temp'}%
\fi\fi
}
% Here is how we actually suppress indentation. Redefine \everypar to
% \kern backwards by \parindent, and then reset itself to empty.
%
% We also make \indent itself not actually do anything until the next
% paragraph.
%
\gdef\dosuppressfirstparagraphindent{%
\gdef\indent{%
\global\let\indent=\ptexindent
\global\everypar = {}%
}%
\global\everypar = {%
\kern-\parindent
\global\let\indent=\ptexindent
\global\everypar = {}%
}%
}%
% @asis just yields its argument. Used with @table, for example.
%
\def\asis#1{#1}
@ -1431,7 +1484,8 @@ where each line of input produces a line of output.}
% \smartitalic{ARG} outputs arg in italics, followed by an italic correction
% unless the following character is such as not to need one.
\def\smartitalicx{\ifx\next,\else\ifx\next-\else\ifx\next.\else\/\fi\fi\fi}
\def\smartitalicx{\ifx\next,\else\ifx\next-\else\ifx\next.\else
\ptexslash\fi\fi\fi}
\def\smartslanted#1{{\ifusingtt\ttsl\sl #1}\futurelet\next\smartitalicx}
\def\smartitalic#1{{\ifusingtt\ttsl\it #1}\futurelet\next\smartitalicx}
@ -1563,7 +1617,7 @@ where each line of input produces a line of output.}
\gdef\kbdexamplefont{\tt}\gdef\kbdfont{\tt}%
\else
\errhelp = \EMsimple
\errmessage{Unknown @kbdinputstyle `\arg'}%
\errmessage{Unknown @kbdinputstyle option `\arg'}%
\fi\fi\fi
}
\def\worddistinct{distinct}
@ -1659,6 +1713,16 @@ where each line of input produces a line of output.}
% @pounds{} is a sterling sign.
\def\pounds{{\it\$}}
% @registeredsymbol - R in a circle. For now, only works in text size;
% we'd have to redo the font mechanism to change the \scriptstyle and
% \scriptscriptstyle font sizes to make it look right in headings.
% Adapted from the plain.tex definition of \copyright.
%
\def\registeredsymbol{%
$^{{\ooalign{\hfil\raise.07ex\hbox{$\scriptstyle\rm R$}\hfil\crcr\Orb}}%
}$%
}
\message{page headings,}
@ -2071,18 +2135,21 @@ where each line of input produces a line of output.}
\itemizey {#1}{\Eitemize}
}
\def\itemizey #1#2{%
\aboveenvbreak %
\itemmax=\itemindent %
\advance \itemmax by -\itemmargin %
\advance \leftskip by \itemindent %
\exdentamount=\itemindent
\parindent = 0pt %
\parskip = \smallskipamount %
\ifdim \parskip=0pt \parskip=2pt \fi%
\def#2{\endgraf\afterenvbreak\endgroup}%
\def\itemcontents{#1}%
\let\item=\itemizeitem}
\def\itemizey#1#2{%
\aboveenvbreak
\itemmax=\itemindent
\advance\itemmax by -\itemmargin
\advance\leftskip by \itemindent
\exdentamount=\itemindent
\parindent=0pt
\parskip=\smallskipamount
\ifdim\parskip=0pt \parskip=2pt \fi
\def#2{\endgraf\afterenvbreak\endgroup}%
\def\itemcontents{#1}%
% @itemize with no arg is equivalent to @itemize @bullet.
\ifx\itemcontents\empty\def\itemcontents{\bullet}\fi
\let\item=\itemizeitem
}
% \splitoff TOKENS\endmark defines \first to be the first token in
% TOKENS, and \rest to be the remainder.
@ -3326,6 +3393,7 @@ width0pt\relax} \fi
%
\smallfonts \rm
\tolerance = 9500
\everypar = {}% don't want the \kern\-parindent from indentation suppression.
\indexbreaks
%
% See if the index file exists and is nonempty.
@ -3707,6 +3775,7 @@ width0pt\relax} \fi
\numberedsubsubseczzz{#2}
\fi
\fi
\suppressfirstparagraphindent
}
% like \numhead, but chooses appendix heading levels
@ -3726,6 +3795,7 @@ width0pt\relax} \fi
\appendixsubsubseczzz{#2}
\fi
\fi
\suppressfirstparagraphindent
}
% like \numhead, but chooses numberless heading levels
@ -3745,6 +3815,7 @@ width0pt\relax} \fi
\unnumberedsubsubseczzz{#2}
\fi
\fi
\suppressfirstparagraphindent
}
% @chapter, @appendix, @unnumbered.
@ -4416,9 +4487,11 @@ width0pt\relax} \fi
\let\equiv=\ptexequiv
\let\!=\ptexexclam
\let\i=\ptexi
\let\indent=\ptexindent
\let\{=\ptexlbrace
\let\+=\tabalign
\let\}=\ptexrbrace
\let\/=\ptexslash
\let\*=\ptexstar
\let\t=\ptext
%
@ -5784,8 +5857,8 @@ width0pt\relax} \fi
% @node's job is to define \lastnode.
\def\node{\ENVcheck\parsearg\nodezzz}
\def\nodezzz#1{\nodexxx [#1,]}
\def\nodexxx[#1,#2]{\gdef\lastnode{#1}}
\def\nodezzz#1{\nodexxx #1,\finishnodeparse}
\def\nodexxx#1,#2\finishnodeparse{\gdef\lastnode{#1}}
\let\nwnode=\node
\let\lastnode=\relax
@ -5913,14 +5986,25 @@ width0pt\relax} \fi
\setbox2 = \hbox{\ignorespaces \refx{#1-snt}{}}%
\ifdim \wd2 > 0pt \refx{#1-snt}\space\fi
}%
% [mynode],
[\printednodename],\space
% page 3
% output the `[mynode]' via a macro.
\xrefprintnodename\printednodename
%
% But we always want a comma and a space:
,\space
%
% output the `page 3'.
\turnoffactive \otherbackslash \putwordpage\tie\refx{#1-pg}{}%
\fi
\endlink
\endgroup}
% This macro is called from \xrefX for the `[nodename]' part of xref
% output. It's a separate macro only so it can be changed more easily,
% since not square brackets don't work in some documents. Particularly
% one that Bob is working on :).
%
\def\xrefprintnodename#1{[#1]}
% \dosetq is called from \setref to do the actual \write (\iflinks).
%
\def\dosetq#1#2{%
@ -6120,13 +6204,14 @@ width0pt\relax} \fi
%
% Auto-number footnotes. Otherwise like plain.
\gdef\footnote{%
\let\indent=\ptexindent
\global\advance\footnoteno by \@ne
\edef\thisfootno{$^{\the\footnoteno}$}%
%
% In case the footnote comes at the end of a sentence, preserve the
% extra spacing after we do the footnote number.
\let\@sf\empty
\ifhmode\edef\@sf{\spacefactor\the\spacefactor}\/\fi
\ifhmode\edef\@sf{\spacefactor\the\spacefactor}\ptexslash\fi
%
% Remove inadvertent blank space before typesetting the footnote number.
\unskip

5
nptl/ChangeLog
View File

@ -1,3 +1,8 @@
2003-05-12 Steven Munroe <sjmunroe@us.ibm.com>
* sysdeps/unix/sysv/linux/powerpc/lowlevellock.h
(lll_mutex_unlock): Use atomic_exchange_rel.
2003-05-11 Ulrich Drepper <drepper@redhat.com>
* cond-perf.c (cons): Add missing locking around setting of alldone.

2
nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h
View File

@ -115,7 +115,7 @@ extern int __lll_timedlock_wait
#define lll_mutex_unlock(lock) \
((void) ({ \
int *__futex = &(lock); \
int __val = atomic_exchange (__futex, 0); \
int __val = atomic_exchange_rel (__futex, 0); \
if (__builtin_expect (__val > 1, 0)) \
lll_futex_wake (__futex, 1); \
}))

87
sysdeps/powerpc/bits/atomic.h
View File

@ -54,27 +54,30 @@ typedef uintmax_t uatomic_max_t;
#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_bool_8_rel(mem, newval, oldval) \
(abort (), 0)
#define __arch_compare_and_exchange_bool_16_rel(mem, newval, oldval) \
(abort (), 0)
#ifdef UP
# define __ARCH_ACQ_INSTR ""
# define __ARCH_REL_INSTR ""
#else
# define __ARCH_ACQ_INSTR "isync"
# define __ARCH_REL_INSTR "sync"
# ifndef __ARCH_REL_INSTR
# define __ARCH_REL_INSTR "sync"
# endif
#endif
#define atomic_full_barrier() __asm ("sync" ::: "memory")
#define atomic_write_barrier() __asm ("eieio" ::: "memory")
/*
* XXX At present these have both acquire and release semantics.
* Ultimately we should do separate _acq and _rel versions.
*/
#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \
__typeof (mem) __memp = (mem); \
__asm __volatile (__ARCH_REL_INSTR "\n" \
__asm __volatile ( \
"1: lwarx %0,0,%1\n" \
" cmpw %0,%2\n" \
" bne 2f\n" \
@ -87,7 +90,38 @@ typedef uintmax_t uatomic_max_t;
__tmp; \
})
#define __arch_atomic_exchange_32(mem, value) \
#define __arch_compare_and_exchange_val_32_rel(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \
__typeof (mem) __memp = (mem); \
__asm __volatile (__ARCH_REL_INSTR "\n" \
"1: lwarx %0,0,%1\n" \
" cmpw %0,%2\n" \
" bne 2f\n" \
" stwcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: " \
: "=&r" (__tmp) \
: "b" (__memp), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp; \
})
#define __arch_atomic_exchange_32_acq(mem, value) \
({ \
__typeof (*mem) __val; \
__asm __volatile ( \
"1: lwarx %0,0,%2\n" \
" stwcx. %3,0,%2\n" \
" bne- 1b\n" \
" " __ARCH_ACQ_INSTR \
: "=&r" (__val), "=m" (*mem) \
: "b" (mem), "r" (value), "1" (*mem) \
: "cr0", "memory"); \
__val; \
})
#define __arch_atomic_exchange_32_rel(mem, value) \
({ \
__typeof (*mem) __val; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
@ -96,7 +130,7 @@ typedef uintmax_t uatomic_max_t;
" bne- 1b" \
: "=&r" (__val), "=m" (*mem) \
: "b" (mem), "r" (value), "1" (*mem) \
: "cr0"); \
: "cr0", "memory"); \
__val; \
})
@ -109,7 +143,7 @@ typedef uintmax_t uatomic_max_t;
" bne- 1b" \
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
: "b" (mem), "r" (value), "2" (*mem) \
: "cr0"); \
: "cr0", "memory"); \
__val; \
})
@ -124,11 +158,10 @@ typedef uintmax_t uatomic_max_t;
"2: " __ARCH_ACQ_INSTR \
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
: "b" (mem), "2" (*mem) \
: "cr0"); \
: "cr0", "memory"); \
__val; \
})
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __result; \
@ -141,13 +174,37 @@ typedef uintmax_t uatomic_max_t;
__result; \
})
#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*mem) == 4) \
__result = __arch_compare_and_exchange_val_32_rel(mem, newval, oldval); \
else if (sizeof (*mem) == 8) \
__result = __arch_compare_and_exchange_val_64_rel(mem, newval, oldval); \
else \
abort (); \
__result; \
})
#define atomic_exchange_acq(mem, value) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*mem) == 4) \
__result = __arch_atomic_exchange_32 (mem, value); \
__result = __arch_atomic_exchange_32_acq (mem, value); \
else if (sizeof (*mem) == 8) \
__result = __arch_atomic_exchange_64 (mem, value); \
__result = __arch_atomic_exchange_64_acq (mem, value); \
else \
abort (); \
__result; \
})
#define atomic_exchange_rel(mem, value) \
({ \
__typeof (*(mem)) __result; \
if (sizeof (*mem) == 4) \
__result = __arch_atomic_exchange_32_rel (mem, value); \
else if (sizeof (*mem) == 8) \
__result = __arch_atomic_exchange_64_rel (mem, value); \
else \
abort (); \
__result; \

31
sysdeps/powerpc/powerpc32/bits/atomic.h
View File

@ -24,7 +24,23 @@
* (a load word and zero (high 32) form). So powerpc64 has a slightly
* different version in sysdeps/powerpc/powerpc64/bits/atomic.h.
*/
# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
({ \
unsigned int __tmp; \
__asm __volatile ( \
"1: lwarx %0,0,%1\n" \
" subf. %0,%2,%0\n" \
" bne 2f\n" \
" stwcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: " __ARCH_ACQ_INSTR \
: "=&r" (__tmp) \
: "b" (mem), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp != 0; \
})
# define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \
({ \
unsigned int __tmp; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
@ -33,7 +49,7 @@
" bne 2f\n" \
" stwcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: " __ARCH_ACQ_INSTR \
"2: " \
: "=&r" (__tmp) \
: "b" (mem), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
@ -51,7 +67,16 @@
# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
# define __arch_atomic_exchange_64(mem, value) \
# define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \
(abort (), 0)
# define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
# define __arch_atomic_exchange_64_acq(mem, value) \
({ abort (); (*mem) = (value); })
# define __arch_atomic_exchange_64_rel(mem, value) \
({ abort (); (*mem) = (value); })
# define __arch_atomic_exchange_and_add_64(mem, value) \

84
sysdeps/powerpc/powerpc64/bits/atomic.h
View File

@ -30,7 +30,7 @@
# define __arch_compare_and_exchange_bool_32_acq(mem, newval, oldval) \
({ \
unsigned int __tmp; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
__asm __volatile ( \
"1: lwarx %0,0,%1\n" \
" extsw %0,%0\n" \
" subf. %0,%2,%0\n" \
@ -44,6 +44,23 @@
__tmp != 0; \
})
# define __arch_compare_and_exchange_bool_32_rel(mem, newval, oldval) \
({ \
unsigned int __tmp; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
"1: lwarx %0,0,%1\n" \
" extsw %0,%0\n" \
" subf. %0,%2,%0\n" \
" bne 2f\n" \
" stwcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: " \
: "=&r" (__tmp) \
: "b" (mem), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp != 0; \
})
/*
* Only powerpc64 processors support Load doubleword and reserve index (ldarx)
* and Store doubleword conditional indexed (stdcx) instructions. So here
@ -52,7 +69,7 @@
# define __arch_compare_and_exchange_bool_64_acq(mem, newval, oldval) \
({ \
unsigned long __tmp; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
__asm __volatile ( \
"1: ldarx %0,0,%1\n" \
" subf. %0,%2,%0\n" \
" bne 2f\n" \
@ -65,11 +82,27 @@
__tmp != 0; \
})
# define __arch_compare_and_exchange_bool_64_rel(mem, newval, oldval) \
({ \
unsigned long __tmp; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
"1: ldarx %0,0,%1\n" \
" subf. %0,%2,%0\n" \
" bne 2f\n" \
" stdcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: " \
: "=&r" (__tmp) \
: "b" (mem), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp != 0; \
})
#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \
__typeof (mem) __memp = (mem); \
__asm __volatile (__ARCH_REL_INSTR "\n" \
__asm __volatile ( \
"1: ldarx %0,0,%1\n" \
" cmpd %0,%2\n" \
" bne 2f\n" \
@ -82,7 +115,38 @@
__tmp; \
})
# define __arch_atomic_exchange_64(mem, value) \
#define __arch_compare_and_exchange_val_64_rel(mem, newval, oldval) \
({ \
__typeof (*(mem)) __tmp; \
__typeof (mem) __memp = (mem); \
__asm __volatile (__ARCH_REL_INSTR "\n" \
"1: ldarx %0,0,%1\n" \
" cmpd %0,%2\n" \
" bne 2f\n" \
" stdcx. %3,0,%1\n" \
" bne- 1b\n" \
"2: " \
: "=&r" (__tmp) \
: "b" (__memp), "r" (oldval), "r" (newval) \
: "cr0", "memory"); \
__tmp; \
})
# define __arch_atomic_exchange_64_acq(mem, value) \
({ \
__typeof (*mem) __val; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
"1: ldarx %0,0,%2\n" \
" stdcx. %3,0,%2\n" \
" bne- 1b\n" \
" " __ARCH_ACQ_INSTR \
: "=&r" (__val), "=m" (*mem) \
: "b" (mem), "r" (value), "1" (*mem) \
: "cr0", "memory"); \
__val; \
})
# define __arch_atomic_exchange_64_rel(mem, value) \
({ \
__typeof (*mem) __val; \
__asm __volatile (__ARCH_REL_INSTR "\n" \
@ -91,7 +155,7 @@
" bne- 1b" \
: "=&r" (__val), "=m" (*mem) \
: "b" (mem), "r" (value), "1" (*mem) \
: "cr0"); \
: "cr0", "memory"); \
__val; \
})
@ -104,7 +168,7 @@
" bne- 1b" \
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
: "b" (mem), "r" (value), "2" (*mem) \
: "cr0"); \
: "cr0", "memory"); \
__val; \
})
@ -119,7 +183,7 @@
"2: " __ARCH_ACQ_INSTR \
: "=&b" (__val), "=&r" (__tmp), "=m" (*mem) \
: "b" (mem), "2" (*mem) \
: "cr0"); \
: "cr0", "memory"); \
__val; \
})
@ -127,6 +191,12 @@
* All powerpc64 processors support the new "light weight" sync (lwsync).
*/
# define atomic_read_barrier() __asm ("lwsync" ::: "memory")
/*
* "light weight" sync can also be used for the release barrier.
*/
# ifndef UP
# define __ARCH_REL_INSTR "lwsync"
# endif
/*
* Include the rest of the atomic ops macros which are common to both