AuroraMiddleware/glibc
1
0
Fork 0
mirror of https://sourceware.org/git/glibc.git synced 2025-01-14 13:00:20 +00:00
Code Issues Packages Projects Releases Wiki Activity

x86_64: Fix svml_d_exp108_core_avx512.S code formatting

Browse Source 
This commit contains following formatting changes

1. Instructions proceeded by a tab.
2. Instruction less than 8 characters in length have a tab
   between it and the first operand.
3. Instruction greater than 7 characters in length have a
   space between it and the first operand.
4. Tabs after `#define`d names and their value.
5. 8 space at the beginning of line replaced by tab.
6. Indent comments with code.
7. Remove redundent .text section.
8. 1 space between line content and line comment.
9. Space after all commas.

Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
This commit is contained in:
Sunil K Pandey 2022-03-07 10:47:12 -08:00
parent e278595a96
commit 7998aecb4d
1 changed files with 212 additions and 213 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
sysdeps/x86_64/fpu/multiarch/svml_d_exp108_core_avx512.S
View File

@ -47,7 +47,6 @@
#include <sysdep.h>
.text
.section .text.evex512, "ax", @progbits
ENTRY(_ZGVeN8v_exp10_skx)
pushq %rbp
@ -226,7 +225,7 @@ typedef struct {
} __svml_dexp10_data_internal_avx512;
#endif
__svml_dexp10_data_internal_avx512:
/*== Exp_tbl_H ==*/
/* Exp_tbl_H */
.quad 0x3ff0000000000000
.quad 0x3ff0b5586cf9890f
.quad 0x3ff172b83c7d517b
@ -243,43 +242,43 @@ __svml_dexp10_data_internal_avx512:
.quad 0x3ffc199bdd85529c
.quad 0x3ffd5818dcfba487
.quad 0x3ffea4afa2a490da
/*== log2(e) ==*/
/* log2(e) */
.align 64
.quad 0x400A934F0979A371, 0x400A934F0979A371, 0x400A934F0979A371, 0x400A934F0979A371, 0x400A934F0979A371, 0x400A934F0979A371, 0x400A934F0979A371, 0x400A934F0979A371
/*== Shifter=2^(52-4)*1.5 ==*/
/* Shifter=2^(52-4)*1.5 */
.align 64
.quad 0x42f8000000003ff0, 0x42f8000000003ff0, 0x42f8000000003ff0, 0x42f8000000003ff0, 0x42f8000000003ff0, 0x42f8000000003ff0, 0x42f8000000003ff0, 0x42f8000000003ff0
/*== L2H = log(2)_high ==*/
/* L2H = log(2)_high */
.align 64
.quad 0x3fd34413509f79ff, 0x3fd34413509f79ff, 0x3fd34413509f79ff, 0x3fd34413509f79ff, 0x3fd34413509f79ff, 0x3fd34413509f79ff, 0x3fd34413509f79ff, 0x3fd34413509f79ff
/*== L2L = log(2)_low ==*/
/* L2L = log(2)_low */
.align 64
.quad 0xbc49dc1da994fd21, 0xbc49dc1da994fd21, 0xbc49dc1da994fd21, 0xbc49dc1da994fd21, 0xbc49dc1da994fd21, 0xbc49dc1da994fd21, 0xbc49dc1da994fd21, 0xbc49dc1da994fd21
/*== EMask ==*/
/* EMask */
.align 64
.quad 0xbfffffffffffffff, 0xbfffffffffffffff, 0xbfffffffffffffff, 0xbfffffffffffffff, 0xbfffffffffffffff, 0xbfffffffffffffff, 0xbfffffffffffffff, 0xbfffffffffffffff
/*== poly_coeff6 ==*/
/* poly_coeff6 */
.align 64
.quad 0x3fcb137ed8ac2020, 0x3fcb137ed8ac2020, 0x3fcb137ed8ac2020, 0x3fcb137ed8ac2020, 0x3fcb137ed8ac2020, 0x3fcb137ed8ac2020, 0x3fcb137ed8ac2020, 0x3fcb137ed8ac2020
/*== poly_coeff5 ==*/
/* poly_coeff5 */
.align 64
.quad 0x3fe141a8e24f9424, 0x3fe141a8e24f9424, 0x3fe141a8e24f9424, 0x3fe141a8e24f9424, 0x3fe141a8e24f9424, 0x3fe141a8e24f9424, 0x3fe141a8e24f9424, 0x3fe141a8e24f9424
/*== poly_coeff4 ==*/
/* poly_coeff4 */
.align 64
.quad 0x3ff2bd77a0926c9d, 0x3ff2bd77a0926c9d, 0x3ff2bd77a0926c9d, 0x3ff2bd77a0926c9d, 0x3ff2bd77a0926c9d, 0x3ff2bd77a0926c9d, 0x3ff2bd77a0926c9d, 0x3ff2bd77a0926c9d
/*== poly_coeff3 ==*/
/* poly_coeff3 */
.align 64
.quad 0x40004705908704c8, 0x40004705908704c8, 0x40004705908704c8, 0x40004705908704c8, 0x40004705908704c8, 0x40004705908704c8, 0x40004705908704c8, 0x40004705908704c8
/*== poly_coeff2 ==*/
/* poly_coeff2 */
.align 64
.quad 0x40053524c73dfe25, 0x40053524c73dfe25, 0x40053524c73dfe25, 0x40053524c73dfe25, 0x40053524c73dfe25, 0x40053524c73dfe25, 0x40053524c73dfe25, 0x40053524c73dfe25
/*== poly_coeff1 ==*/
/* poly_coeff1 */
.align 64
.quad 0x40026bb1bbb554c2, 0x40026bb1bbb554c2, 0x40026bb1bbb554c2, 0x40026bb1bbb554c2, 0x40026bb1bbb554c2, 0x40026bb1bbb554c2, 0x40026bb1bbb554c2, 0x40026bb1bbb554c2
/*== AbsMask ==*/
/* AbsMask */
.align 64
.quad 0x7fffffffffffffff, 0x7fffffffffffffff, 0x7fffffffffffffff, 0x7fffffffffffffff, 0x7fffffffffffffff, 0x7fffffffffffffff, 0x7fffffffffffffff, 0x7fffffffffffffff
/*== Threshold ==*/
/* Threshold */
.align 64
.quad 0x40733A7146F72A41, 0x40733A7146F72A41, 0x40733A7146F72A41, 0x40733A7146F72A41, 0x40733A7146F72A41, 0x40733A7146F72A41, 0x40733A7146F72A41, 0x40733A7146F72A41
.align 64