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PowerPC floating point little-endian [12 of 15]
http://sourceware.org/ml/libc-alpha/2013-08/msg00087.html Fixes for little-endian in 32-bit assembly. * sysdeps/powerpc/sysdep.h (LOWORD, HIWORD, HISHORT): Define. * sysdeps/powerpc/powerpc32/fpu/s_copysign.S: Load little-endian words of double from correct stack offsets. * sysdeps/powerpc/powerpc32/fpu/s_copysignl.S: Likewise. * sysdeps/powerpc/powerpc32/fpu/s_lrint.S: Likewise. * sysdeps/powerpc/powerpc32/fpu/s_lround.S: Likewise. * sysdeps/powerpc/powerpc32/power4/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc32/power4/fpu/s_llrintf.S: Likewise. * sysdeps/powerpc/powerpc32/power5+/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc32/power5+/fpu/s_lround.S: Likewise. * sysdeps/powerpc/powerpc32/power5/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc32/power6/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S: Likewise. * sysdeps/powerpc/powerpc32/power6/fpu/s_llrintf.S: Likewise. * sysdeps/powerpc/powerpc32/power6/fpu/s_llround.S: Likewise. * sysdeps/powerpc/powerpc32/power7/fpu/s_finite.S: Likewise. * sysdeps/powerpc/powerpc32/power7/fpu/s_isinf.S: Likewise. * sysdeps/powerpc/powerpc32/power7/fpu/s_isnan.S: Likewise. * sysdeps/powerpc/powerpc64/power7/fpu/s_finite.S: Use HISHORT. * sysdeps/powerpc/powerpc64/power7/fpu/s_isinf.S: Likewise.
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Alan Modra
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23
ChangeLog
23
ChangeLog
@ -1,3 +1,26 @@
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2013-10-04 Alan Modra <amodra@gmail.com>
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* sysdeps/powerpc/sysdep.h (LOWORD, HIWORD, HISHORT): Define.
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* sysdeps/powerpc/powerpc32/fpu/s_copysign.S: Load little-endian
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words of double from correct stack offsets.
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* sysdeps/powerpc/powerpc32/fpu/s_copysignl.S: Likewise.
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* sysdeps/powerpc/powerpc32/fpu/s_lrint.S: Likewise.
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* sysdeps/powerpc/powerpc32/fpu/s_lround.S: Likewise.
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* sysdeps/powerpc/powerpc32/power4/fpu/s_llrint.S: Likewise.
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* sysdeps/powerpc/powerpc32/power4/fpu/s_llrintf.S: Likewise.
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* sysdeps/powerpc/powerpc32/power5+/fpu/s_llround.S: Likewise.
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* sysdeps/powerpc/powerpc32/power5+/fpu/s_lround.S: Likewise.
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* sysdeps/powerpc/powerpc32/power5/fpu/s_isnan.S: Likewise.
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* sysdeps/powerpc/powerpc32/power6/fpu/s_isnan.S: Likewise.
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* sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S: Likewise.
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* sysdeps/powerpc/powerpc32/power6/fpu/s_llrintf.S: Likewise.
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* sysdeps/powerpc/powerpc32/power6/fpu/s_llround.S: Likewise.
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* sysdeps/powerpc/powerpc32/power7/fpu/s_finite.S: Likewise.
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* sysdeps/powerpc/powerpc32/power7/fpu/s_isinf.S: Likewise.
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* sysdeps/powerpc/powerpc32/power7/fpu/s_isnan.S: Likewise.
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* sysdeps/powerpc/powerpc64/power7/fpu/s_finite.S: Use HISHORT.
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* sysdeps/powerpc/powerpc64/power7/fpu/s_isinf.S: Likewise.
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2013-10-04 Alan Modra <amodra@gmail.com>
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* sysdeps/powerpc/fpu_control.h (_FPU_GETCW): Rewrite using
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@ -29,7 +29,7 @@ ENTRY(__copysign)
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stwu r1,-16(r1)
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cfi_adjust_cfa_offset (16)
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stfd fp2,8(r1)
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lwz r3,8(r1)
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lwz r3,8+HIWORD(r1)
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cmpwi r3,0
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addi r1,r1,16
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cfi_adjust_cfa_offset (-16)
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@ -30,7 +30,7 @@ ENTRY(__copysignl)
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fmr fp0,fp1
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fabs fp1,fp1
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fcmpu cr7,fp0,fp1
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lwz r3,8(r1)
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lwz r3,8+HIWORD(r1)
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cmpwi cr6,r3,0
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addi r1,r1,16
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cfi_adjust_cfa_offset (-16)
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@ -24,10 +24,10 @@ ENTRY (__lrint)
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stwu r1,-16(r1)
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fctiw fp13,fp1
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stfd fp13,8(r1)
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nop /* Insure the following load is in a different dispatch group */
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nop /* Ensure the following load is in a different dispatch group */
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nop /* to avoid pipe stall on POWER4&5. */
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nop
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lwz r3,12(r1)
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lwz r3,8+LOWORD(r1)
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addi r1,r1,16
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blr
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END (__lrint)
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@ -67,7 +67,7 @@ ENTRY (__lround)
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nop /* Ensure the following load is in a different dispatch */
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nop /* group to avoid pipe stall on POWER4&5. */
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nop
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lwz r3,12(r1) /* Load return as integer. */
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lwz r3,8+LOWORD(r1) /* Load return as integer. */
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.Lout:
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addi r1,r1,16
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blr
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@ -29,8 +29,8 @@ ENTRY (__llrint)
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nop /* Insure the following load is in a different dispatch group */
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nop /* to avoid pipe stall on POWER4&5. */
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nop
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lwz r3,8(r1)
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lwz r4,12(r1)
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lwz r3,8+HIWORD(r1)
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lwz r4,8+LOWORD(r1)
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addi r1,r1,16
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blr
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END (__llrint)
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@ -28,8 +28,8 @@ ENTRY (__llrintf)
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nop /* Insure the following load is in a different dispatch group */
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nop /* to avoid pipe stall on POWER4&5. */
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nop
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lwz r3,8(r1)
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lwz r4,12(r1)
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lwz r3,8+HIWORD(r1)
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lwz r4,8+LOWORD(r1)
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addi r1,r1,16
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blr
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END (__llrintf)
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@ -39,8 +39,8 @@ ENTRY (__llround)
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nop /* Ensure the following load is in a different dispatch */
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nop /* group to avoid pipe stall on POWER4&5. */
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nop
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lwz r4,12(r1)
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lwz r3,8(r1)
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lwz r3,8+HIWORD(r1)
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lwz r4,8+LOWORD(r1)
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addi r1,r1,16
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blr
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END (__llround)
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@ -38,7 +38,7 @@ ENTRY (__lround)
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nop /* Ensure the following load is in a different dispatch */
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nop /* group to avoid pipe stall on POWER4&5. */
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nop
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lwz r3,12(r1)
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lwz r3,8+LOWORD(r1)
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addi r1,r1,16
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blr
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END (__lround)
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@ -27,8 +27,8 @@ EALIGN (__isnan, 4, 0)
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ori r1,r1,0
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stfd fp1,24(r1) /* copy FPR to GPR */
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ori r1,r1,0
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lwz r4,24(r1)
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lwz r5,28(r1)
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lwz r4,24+HIWORD(r1)
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lwz r5,24+LOWORD(r1)
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lis r0,0x7ff0 /* const long r0 0x7ff00000 00000000 */
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clrlwi r4,r4,1 /* x = fabs(x) */
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cmpw cr7,r4,r0 /* if (fabs(x) =< inf) */
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@ -27,8 +27,8 @@ EALIGN (__isnan, 4, 0)
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ori r1,r1,0
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stfd fp1,24(r1) /* copy FPR to GPR */
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ori r1,r1,0
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lwz r4,24(r1)
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lwz r5,28(r1)
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lwz r4,24+HIWORD(r1)
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lwz r5,24+LOWORD(r1)
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lis r0,0x7ff0 /* const long r0 0x7ff00000 00000000 */
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clrlwi r4,r4,1 /* x = fabs(x) */
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cmpw cr7,r4,r0 /* if (fabs(x) =< inf) */
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@ -29,8 +29,8 @@ ENTRY (__llrint)
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/* Insure the following load is in a different dispatch group by
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inserting "group ending nop". */
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ori r1,r1,0
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lwz r3,8(r1)
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lwz r4,12(r1)
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lwz r3,8+HIWORD(r1)
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lwz r4,8+LOWORD(r1)
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addi r1,r1,16
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blr
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END (__llrint)
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@ -28,8 +28,8 @@ ENTRY (__llrintf)
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/* Insure the following load is in a different dispatch group by
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inserting "group ending nop". */
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ori r1,r1,0
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lwz r3,8(r1)
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lwz r4,12(r1)
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lwz r3,8+HIWORD(r1)
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lwz r4,8+LOWORD(r1)
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addi r1,r1,16
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blr
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END (__llrintf)
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@ -39,8 +39,8 @@ ENTRY (__llround)
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/* Insure the following load is in a different dispatch group by
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inserting "group ending nop". */
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ori r1,r1,0
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lwz r4,12(r1)
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lwz r3,8(r1)
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lwz r3,8+HIWORD(r1)
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lwz r4,8+LOWORD(r1)
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addi r1,r1,16
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blr
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END (__llround)
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@ -54,9 +54,8 @@ ENTRY (__finite)
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stfd fp1,8(r1) /* Transfer FP to GPR's. */
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ori 2,2,0 /* Force a new dispatch group. */
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lhz r0,8(r1) /* Fetch the upper portion of the high word of
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the FP value (where the exponent and sign bits
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are). */
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lhz r0,8+HISHORT(r1) /* Fetch the upper 16 bits of the FP value
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(biased exponent and sign bit). */
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clrlwi r0,r0,17 /* r0 = abs(r0). */
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addi r1,r1,16 /* Reset the stack pointer. */
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cmpwi cr7,r0,0x7ff0 /* r4 == 0x7ff0?. */
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@ -48,14 +48,13 @@ ENTRY (__isinf)
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li r3,0
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bflr 29 /* If not INF, return. */
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/* Either we have -INF/+INF or a denormal. */
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/* Either we have +INF or -INF. */
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stwu r1,-16(r1) /* Allocate stack space. */
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stfd fp1,8(r1) /* Transfer FP to GPR's. */
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ori 2,2,0 /* Force a new dispatch group. */
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lhz r4,8(r1) /* Fetch the upper portion of the high word of
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the FP value (where the exponent and sign bits
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are). */
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lhz r4,8+HISHORT(r1) /* Fetch the upper 16 bits of the FP value
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(biased exponent and sign bit). */
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addi r1,r1,16 /* Reset the stack pointer. */
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cmpwi cr7,r4,0x7ff0 /* r4 == 0x7ff0? */
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li r3,1
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@ -53,8 +53,8 @@ ENTRY (__isnan)
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stwu r1,-16(r1) /* Allocate stack space. */
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stfd fp1,8(r1) /* Transfer FP to GPR's. */
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ori 2,2,0 /* Force a new dispatch group. */
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lwz r4,8(r1) /* Load the upper half of the FP value. */
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lwz r5,12(r1) /* Load the lower half of the FP value. */
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lwz r4,8+HIWORD(r1) /* Load the upper half of the FP value. */
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lwz r5,8+LOWORD(r1) /* Load the lower half of the FP value. */
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addi r1,r1,16 /* Reset the stack pointer. */
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lis r0,0x7ff0 /* Load the upper portion for an INF/NaN. */
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clrlwi r4,r4,1 /* r4 = abs(r4). */
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@ -39,10 +39,8 @@ EALIGN (__finite, 4, 0)
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stfd fp1,-16(r1) /* Transfer FP to GPR's. */
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ori 2,2,0 /* Force a new dispatch group. */
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lhz r4,-16(r1) /* Fetch the upper portion of the high word of
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the FP value (where the exponent and sign bits
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are). */
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lhz r4,-16+HISHORT(r1) /* Fetch the upper 16 bits of the FP value
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(biased exponent and sign bit). */
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clrlwi r4,r4,17 /* r4 = abs(r4). */
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cmpwi cr7,r4,0x7ff0 /* r4 == 0x7ff0? */
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bltlr cr7 /* LT means finite, other non-finite. */
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@ -38,9 +38,8 @@ EALIGN (__isinf, 4, 0)
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stfd fp1,-16(r1) /* Transfer FP to GPR's. */
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ori 2,2,0 /* Force a new dispatch group. */
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lhz r4,-16(r1) /* Fetch the upper portion of the high word of
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the FP value (where the exponent and sign bits
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are). */
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lhz r4,-16+HISHORT(r1) /* Fetch the upper 16 bits of the FP value
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(biased exponent and sign bit). */
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cmpwi cr7,r4,0x7ff0 /* r4 == 0x7ff0? */
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li r3,1
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beqlr cr7 /* EQ means INF, otherwise -INF. */
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@ -144,6 +144,21 @@
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#define VRSAVE 256
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/* The 32-bit words of a 64-bit dword are at these offsets in memory. */
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#if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN
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# define LOWORD 0
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# define HIWORD 4
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#else
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# define LOWORD 4
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# define HIWORD 0
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#endif
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/* The high 16-bit word of a 64-bit dword is at this offset in memory. */
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#if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN
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# define HISHORT 6
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#else
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# define HISHORT 0
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#endif
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/* This seems to always be the case on PPC. */
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#define ALIGNARG(log2) log2
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