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Alpha ev6 memset implementation.
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Ulrich Drepper
parent
ba26d0334e
commit
7c688d0100
224
sysdeps/alpha/alphaev6/memset.S
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224
sysdeps/alpha/alphaev6/memset.S
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/* Copyright (C) 2000 Free Software Foundation, Inc.
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Contributed by Richard Henderson (rth@tamu.edu)
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EV6 optimized by Rick Gorton <rick.gorton@alpha-processor.com>.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Library General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Library General Public License for more details.
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You should have received a copy of the GNU Library General Public
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License along with the GNU C Library; see the file COPYING.LIB. If not,
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write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include <sysdep.h>
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.arch ev6
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.set noat
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.set noreorder
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ENTRY(memset)
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#ifdef PROF
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ldgp gp, 0(pv)
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lda AT, _mcount
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jsr AT, (AT), _mcount
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.prologue 1
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#else
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.prologue 0
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#endif
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/*
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* Serious stalling happens. The only way to mitigate this is to
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* undertake a major re-write to interleave the constant materialization
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* with other parts of the fall-through code. This is important, even
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* though it makes maintenance tougher.
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* Do this later.
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*/
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and $17, 255, $1 # E : 00000000000000ch
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insbl $17, 1, $2 # U : 000000000000ch00
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mov $16, $0 # E : return value
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ble $18, $end # U : zero length requested?
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addq $18, $16, $6 # E : max address to write to
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or $1, $2, $17 # E : 000000000000chch
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insbl $1, 2, $3 # U : 0000000000ch0000
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insbl $1, 3, $4 # U : 00000000ch000000
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or $3, $4, $3 # E : 00000000chch0000
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inswl $17, 4, $5 # U : 0000chch00000000
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xor $16, $6, $1 # E : will complete write be within one quadword?
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inswl $17, 6, $2 # U : chch000000000000
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or $17, $3, $17 # E : 00000000chchchch
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or $2, $5, $2 # E : chchchch00000000
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bic $1, 7, $1 # E : fit within a single quadword?
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and $16, 7, $3 # E : Target addr misalignment
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or $17, $2, $17 # E : chchchchchchchch
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beq $1, $within_quad # U :
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nop # E :
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beq $3, $aligned # U : target is 0mod8
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/*
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* Target address is misaligned, and won't fit within a quadword.
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*/
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ldq_u $4, 0($16) # L : Fetch first partial
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mov $16, $5 # E : Save the address
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insql $17, $16, $2 # U : Insert new bytes
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subq $3, 8, $3 # E : Invert (for addressing uses)
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addq $18, $3, $18 # E : $18 is new count ($3 is negative)
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mskql $4, $16, $4 # U : clear relevant parts of the quad
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subq $16, $3, $16 # E : $16 is new aligned destination
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or $2, $4, $1 # E : Final bytes
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nop
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stq_u $1,0($5) # L : Store result
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nop
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nop
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.align 4
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$aligned:
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/*
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* We are now guaranteed to be quad aligned, with at least
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* one partial quad to write.
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*/
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sra $18, 3, $3 # U : Number of remaining quads to write
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and $18, 7, $18 # E : Number of trailing bytes to write
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mov $16, $5 # E : Save dest address
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beq $3, $no_quad # U : tail stuff only
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/*
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* It's worth the effort to unroll this and use wh64 if possible.
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* At this point, entry values are:
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* $16 Current destination address
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* $5 A copy of $16
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* $6 The max quadword address to write to
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* $18 Number trailer bytes
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* $3 Number quads to write
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*/
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and $16, 0x3f, $2 # E : Forward work (only useful for unrolled loop)
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subq $3, 16, $4 # E : Only try to unroll if > 128 bytes
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subq $2, 0x40, $1 # E : bias counter (aligning stuff 0mod64)
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blt $4, $loop # U :
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/*
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* We know we've got at least 16 quads, minimum of one trip
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* through unrolled loop. Do a quad at a time to get us 0mod64
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* aligned.
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*/
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nop # E :
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nop # E :
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nop # E :
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beq $1, $bigalign # U :
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$alignmod64:
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stq $17, 0($5) # L :
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subq $3, 1, $3 # E : For consistency later
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addq $1, 8, $1 # E : Increment towards zero for alignment
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addq $5, 8, $4 # E : Initial wh64 address (filler instruction)
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nop
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nop
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addq $5, 8, $5 # E : Inc address
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blt $1, $alignmod64 # U :
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$bigalign:
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/*
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* $3 - number quads left to go
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* $5 - target address (aligned 0mod64)
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* $17 - mask of stuff to store
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* Scratch registers available: $7, $2, $4, $1
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* We know that we'll be taking a minimum of one trip through.
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* CWG Section 3.7.6: do not expect a sustained store rate of > 1/cycle
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* Assumes the wh64 needs to be for 2 trips through the loop in the future.
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* The wh64 is issued on for the starting destination address for trip +2
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* through the loop, and if there are less than two trips left, the target
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* address will be for the current trip.
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*/
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$do_wh64:
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wh64 ($4) # L1 : memory subsystem write hint
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subq $3, 24, $2 # E : For determining future wh64 addresses
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stq $17, 0($5) # L :
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nop # E :
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addq $5, 128, $4 # E : speculative target of next wh64
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stq $17, 8($5) # L :
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stq $17, 16($5) # L :
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addq $5, 64, $7 # E : Fallback address for wh64 (== next trip addr)
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stq $17, 24($5) # L :
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stq $17, 32($5) # L :
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cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
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nop
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stq $17, 40($5) # L :
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stq $17, 48($5) # L :
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subq $3, 16, $2 # E : Repeat the loop at least once more?
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nop
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stq $17, 56($5) # L :
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addq $5, 64, $5 # E :
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subq $3, 8, $3 # E :
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bge $2, $do_wh64 # U :
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nop
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nop
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nop
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beq $3, $no_quad # U : Might have finished already
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.align 4
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/*
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* Simple loop for trailing quadwords, or for small amounts
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* of data (where we can't use an unrolled loop and wh64)
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*/
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$loop:
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stq $17, 0($5) # L :
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subq $3, 1, $3 # E : Decrement number quads left
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addq $5, 8, $5 # E : Inc address
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bne $3, $loop # U : more?
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$no_quad:
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/*
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* Write 0..7 trailing bytes.
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*/
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nop # E :
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beq $18, $end # U : All done?
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ldq $7, 0($5) # L :
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mskqh $7, $6, $2 # U : Mask final quad
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insqh $17, $6, $4 # U : New bits
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or $2, $4, $1 # E : Put it all together
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stq $1, 0($5) # L : And back to memory
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ret $31,($26),1 # L0 :
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$within_quad:
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ldq_u $1, 0($16) # L :
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insql $17, $16, $2 # U : New bits
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mskql $1, $16, $4 # U : Clear old
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or $2, $4, $2 # E : New result
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mskql $2, $6, $4 # U :
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mskqh $1, $6, $2 # U :
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or $2, $4, $1 # E :
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stq_u $1, 0($16) # L :
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$end:
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nop
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nop
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nop
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ret $31,($26),1 # L0 :
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END(memset)
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