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Fix ARM NAN fraction bits.

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Current ARM soft-float implementation is violating the RTABI
(http://infocenter.arm.com/help/topic/com.arm.doc.ihi0043d/IHI0043D_rtabi.pdf)
Section 4.1.1.1:

When not otherwise specified by IEEE 754, the result on an invalid
operation should be the quiet NaN bit pattern with only the most
significant bit of the significand set, and all other significand bits
zero.

This patch fixes it by setting _FP_NANFRAC_* to zero.

Ran make check test with -mfloat-abi=soft. No regression.

	* sysdeps/arm/soft-fp/sfp-machine.h (_FP_NANFRAC_S, _FP_NANFRAC_D)
	(_FP_NANFRAC_Q): Set to zero.
This commit is contained in:
Joey Ye 2014-02-27 17:44:43 +00:00 committed by Joseph Myers
parent 2b7f4f2cad
commit 7d92b78723
2 changed files with 8 additions and 3 deletions
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5
ChangeLog
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@ -1,3 +1,8 @@
2014-02-27 Joey Ye <joey.ye@arm.com>
* sysdeps/arm/soft-fp/sfp-machine.h (_FP_NANFRAC_S, _FP_NANFRAC_D)
(_FP_NANFRAC_Q): Set to zero.
2014-02-27 Siddhesh Poyarekar <siddhesh@redhat.com>
[BZ #16623]

6
sysdeps/arm/soft-fp/sfp-machine.h
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@ -21,9 +21,9 @@
#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
#define _FP_NANFRAC_S 0
#define _FP_NANFRAC_D 0, 0
#define _FP_NANFRAC_Q 0, 0, 0, 0
#define _FP_NANSIGN_S 0
#define _FP_NANSIGN_D 0
#define _FP_NANSIGN_Q 0