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sparc: Use ba,a,pt in PLTs and fix bugs in R_SPARC_JMP_IREL handling.
2010-03-03 David S. Miller <davem@davemloft.net> * sysdeps/sparc/sparc32/dl-machine.h (elf_machine_lazy_rel): Must pass '1' for 't' argument to sparc_fixup_plt. * sysdeps/sparc/sparc64/dl-machine.h (elf_machine_lazy_rel): Likewise. * sysdeps/sparc/sparc32/dl-plt.h (OPCODE_BA_PT): Define. (sparc_fixup_plt): Document 't' argument. Enable branch optimization and use v9 branches when possible. Explain why we cannot unconditionally patch the branch into the first PLT instruction. * sysdeps/sparc/sparc64/dl-plt.h (sparc64_fixup_plt): Document 't' argument. Use v9 branches when possible. Explain why we can in fact unconditionally use a branch in the first PLT instruction here.
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David S. Miller
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ChangeLog
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ChangeLog
@ -1,3 +1,19 @@
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2010-03-03 David S. Miller <davem@davemloft.net>
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* sysdeps/sparc/sparc32/dl-machine.h (elf_machine_lazy_rel): Must
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pass '1' for 't' argument to sparc_fixup_plt.
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* sysdeps/sparc/sparc64/dl-machine.h (elf_machine_lazy_rel):
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Likewise.
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* sysdeps/sparc/sparc32/dl-plt.h (OPCODE_BA_PT): Define.
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(sparc_fixup_plt): Document 't' argument. Enable branch
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optimization and use v9 branches when possible. Explain why we
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cannot unconditionally patch the branch into the first PLT
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instruction.
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* sysdeps/sparc/sparc64/dl-plt.h (sparc64_fixup_plt): Document 't'
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argument. Use v9 branches when possible. Explain why we can in
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fact unconditionally use a branch in the first PLT instruction
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here.
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2010-02-28 Roland McGrath <roland@redhat.com>
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* elf/elf.h (NT_X86_XSTATE): New macro.
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@ -563,7 +563,7 @@ elf_machine_lazy_rel (struct link_map *map,
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{
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Elf32_Addr value = map->l_addr + reloc->r_addend;
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value = ((Elf32_Addr (*) (void)) value) ();
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sparc_fixup_plt (reloc, reloc_addr, value, 0, 1);
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sparc_fixup_plt (reloc, reloc_addr, value, 1, 1);
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}
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else if (r_type == R_SPARC_NONE)
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;
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@ -25,19 +25,55 @@
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#define OPCODE_JMP_G1 0x81c06000 /* jmp %g1+?; add lo 10 bits of value */
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#define OPCODE_SAVE_SP 0x9de3bfa8 /* save %sp, -(16+6)*4, %sp */
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#define OPCODE_BA 0x30800000 /* b,a ?; add PC-rel word address */
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#define OPCODE_BA_PT 0x30480000 /* ba,a,pt %icc, ?; add PC-rel word address */
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static inline __attribute__ ((always_inline)) Elf32_Addr
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sparc_fixup_plt (const Elf32_Rela *reloc, Elf32_Addr *reloc_addr,
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Elf32_Addr value, int t, int do_flush)
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{
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Elf32_Sword disp = value - (Elf32_Addr) reloc_addr;
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Elf32_Sword disp;
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if (0 && disp >= -0x800000 && disp < 0x800000)
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/* 't' is '0' if we are resolving this PLT entry for RTLD bootstrap,
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in which case we'll be resolving all PLT entries and thus can
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optimize by overwriting instructions starting at the first PLT entry
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instruction and we need not be mindful of thread safety.
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Otherwise, 't' is '1'. */
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reloc_addr += t;
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disp = value - (Elf32_Addr) reloc_addr;
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if (disp >= -0x800000 && disp < 0x800000)
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{
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/* Don't need to worry about thread safety. We're writing just one
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instruction. */
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unsigned int insn = OPCODE_BA | ((disp >> 2) & 0x3fffff);
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reloc_addr[0] = OPCODE_BA | ((disp >> 2) & 0x3fffff);
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#ifdef __sparc_v9__
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/* On V9 we can do even better by using a branch with
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prediction if we fit into the even smaller 19-bit
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displacement field. */
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if (disp >= -0x100000 && disp < 0x100000)
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insn = OPCODE_BA_PT | ((disp >> 2) & 0x07ffff);
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#endif
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/* Even if we are writing just a single branch, we must not
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ignore the 't' offset. Consider a case where we have some
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PLT slots which can be optimized into a single branch and
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some which cannot. Then we can end up with a PLT which looks
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like:
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PLT4.0: sethi %(PLT_4_INDEX), %g1
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sethi %(fully_resolved_sym_4), %g1
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jmp %g1 + %lo(fully_resolved_sym_4)
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PLT5.0: ba,a fully_resolved_sym_5
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ba,a PLT0.0
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...
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The delay slot of that jmp must always be either a sethi to
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%g1 or a nop. But if we try to place this displacement
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branch there, PLT4.0 will jump to fully_resolved_sym_4 for 1
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instruction and then go immediately to
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fully_resolved_sym_5. */
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reloc_addr[0] = insn;
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if (do_flush)
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__asm __volatile ("flush %0" : : "r"(reloc_addr));
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}
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@ -48,7 +84,6 @@ sparc_fixup_plt (const Elf32_Rela *reloc, Elf32_Addr *reloc_addr,
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need not be done during bootstrapping, since there are no threads.
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But we also can't tell if we _can_ use flush, so don't. */
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reloc_addr += t;
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reloc_addr[1] = OPCODE_JMP_G1 | (value & 0x3ff);
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if (do_flush)
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__asm __volatile ("flush %0+4" : : "r"(reloc_addr));
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@ -661,7 +661,7 @@ elf_machine_lazy_rel (struct link_map *map,
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{
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/* 'high' is always zero, for large PLT entries the linker
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emits an R_SPARC_IRELATIVE. */
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sparc64_fixup_plt (map, reloc, reloc_addr, value, 0, 0);
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sparc64_fixup_plt (map, reloc, reloc_addr, value, 0, 1);
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}
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else
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*reloc_addr = value;
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@ -28,7 +28,14 @@ sparc64_fixup_plt (struct link_map *map, const Elf64_Rela *reloc,
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Elf64_Addr plt_vaddr = (Elf64_Addr) reloc_addr;
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Elf64_Sxword disp = value - plt_vaddr;
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/* Now move plt_vaddr up to the call instruction. */
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/* 't' is '0' if we are resolving this PLT entry for RTLD bootstrap,
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in which case we'll be resolving all PLT entries and thus can
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optimize by overwriting instructions starting at the first PLT entry
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instruction and we need not be mindful of thread safety.
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Otherwise, 't' is '1'.
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Now move plt_vaddr up to the call instruction. */
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plt_vaddr += ((t + 1) * 4);
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/* PLT entries .PLT32768 and above look always the same. */
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@ -39,10 +46,22 @@ sparc64_fixup_plt (struct link_map *map, const Elf64_Rela *reloc,
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/* Near destination. */
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else if (disp >= -0x800000 && disp < 0x800000)
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{
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/* As this is just one instruction, it is thread safe and so
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we can avoid the unnecessary sethi FOO, %g1.
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b,a target */
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insns[0] = 0x30800000 | ((disp >> 2) & 0x3fffff);
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unsigned int insn;
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/* ba,a */
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insn = 0x30800000 | ((disp >> 2) & 0x3fffff);
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if (disp >= -0x100000 && disp < 0x100000)
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{
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/* ba,a,pt %icc */
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insn = 0x30480000 | ((disp >> 2) & 0x07ffff);
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}
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/* As this is just one instruction, it is thread safe and so we
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can avoid the unnecessary sethi FOO, %g1. Each 64-bit PLT
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entry is 8 instructions long, so we can't run into the 'jmp'
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delay slot problems 32-bit PLTs can. */
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insns[0] = insn;
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__asm __volatile ("flush %0" : : "r" (insns));
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}
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/* 32-bit Sparc style, the target is in the lower 32-bits of
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